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  brushless dc motor flash type 8-bit mcu HT66FM5230 revision: v1.00 date: ? a ? 1 ?? ? 01 ? ? a ? 1 ?? ? 01 ?
rev. 1.00 ? ? a ? 1 ?? ? 01 ? rev. 1.00 ? ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu table of contents eates cpu features ......................................................................................................................... 7 peripheral features ................................................................................................................. 7 general description ......................................................................................... 8 block diagram .................................................................................................. 8 pin assignment ........... ..................................................................................... 9 pin descriptions ............................................................................................ 10 absolute ?aximum ratings .......................................................................... 1? d.c. characteristics ....................................................................................... 1? a.c. characteristics ....................................................................................... 1? hirc frequenc ? accurac ? over device v dd and temperature ............. ................................ 1 ? a/d converter characteristics ........... ........................................................... 14 d/a converter characteristics ...................................................................... 14 8-bit r-?r d/a converter (analog conditon v dd =5v? c l =10pf) ................. 15 operational amplifer characteristics clocking and pipelining ......................................................................................................... 17 program counter ................................................................................................................... 18 stack ..................................................................................................................................... 19 arithmetic and logic unit C alu ........................................................................................... 19 flash program ?emor? ................................................................................. ?0 structure ................................................................................................................................ ? 0 special vectors ..................................................................................................................... ? 0 look-up table ............. ........................................................................................................... ? 0 table program example ........................................................................................................ ? 1 in circuit programming ......................................................................................................... ?? on-chip debug support C ocds ......................................................................................... ?? ra? data ?emor? ......................................................................................... ?? structure ................................................................................................................................ ?? special function register description ........................................................ ?5 indirect addressing registers C iar0 ? iar1 ......................................................................... ? 5 ? emor ? pointers C ? p0 ? ? p1 .............................................................................................. ? 5 bank pointer C bp ................................................................................................................. ? 6 accumulator C acc ............................................................................................................... ? 6 program counter low register C pcl .................................................................................. ? 6 look-up table registers C tblp ? tbhp ? tblh ..................................................................... ? 6 status register C status .................................................................................................... ? 7
rev. 1.00 ? ?a? 1?? ?01? rev. 1.00 ? ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu eeprom data memory ........... ....................................................................... 29 eepro ? data ? emor ? structure ........................................................................................ ? 9 eepro ? registers ............ .................................................................................................. ? 9 reading data from the eepro ? ........................................................................................ ? 1 writing data to the eepro ? ................................................................................................ ? 1 write protection ..................................................................................................................... ? 1 eepro ? interrupt ............. ................................................................................................... ? 1 programming considerations ............. ................................................................................... ? 1 oscillator ........................................................................................................ 33 oscillator overview ............. .................................................................................................. ?? system clock confgurations ................................................................................................ ?? internal ? 0 ? hz rc oscillator C hirc ................................................................................... ? 4 internal ?? khz oscillator C lirc ........................................................................................... ? 4 supplementar ? clocks .......................................................................................................... ? 4 operating modes and system clocks ......................................................... 35 s ? stem clocks ...................................................................................................................... ? 5 s ? stem operation ? odes ...................................................................................................... ? 6 control register .................................................................................................................... ? 7 operating ? ode switching ................................................................................................... ? 9 nor ? al ? ode to slow ? ode switching ........................................................................... ? 9 slow ? ode to nor ? al ? ode switching .......................................................................... ? 9 entering the sleep ? ode .................................................................................................... 41 entering the idle0 ? ode ...................................................................................................... 41 entering the idle1 ? ode ...................................................................................................... 41 standb ? current considerations ........................................................................................... 4 ? wake-up ................................................................................................................................ 4 ? watchdog timer ........... .................................................................................. 43 watchdog timer clock source .............................................................................................. 4 ? watchdog timer control register ............. ............................................................................ 4 ? watchdog timer operation ................................................................................................... 44 reset and initialisation .................................................................................. 45 reset functions ............. ....................................................................................................... 45 reset initial conditions ......................................................................................................... 47 input/output ports ......................................................................................... 51 i/o register list .................................................................................................................... 51 pull-high resistors ................................................................................................................ 51 port a wake-up ............. ........................................................................................................ 5 ? i/o port control registers ..................................................................................................... 5 ? pin-sharing functions ........................................................................................................... 54 pin-remapping functions ...................................................................................................... 56 pin-remapping registers ....................................................................................................... 56 i/o pin structures .................................................................................................................. 57 programming considerations ............. ................................................................................... 58
rev. 1.00 4 ? a ? 1 ?? ? 01 ? rev. 1.00 5 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu timer modules C tm .......... ............................................................................ 58 introduction ........................................................................................................................... 58 t ? operation ............. ........................................................................................................... 59 t ? clock source ............. ...................................................................................................... 59 t ? interrupts ......................................................................................................................... 59 t ? external pins ................................................................................................................... 59 programming considerations ............. ................................................................................... 60 compact type tm C ctm .............................................................................. 61 compact t ? operation ......................................................................................................... 61 compact t ? pe t ? register description ................................................................................ 6 ? compact t ? pe t ? operating ? odes .................................................................................... 70 compare ? atch output ? ode ............................................................................................... 70 timer/counter ? ode ............................................................................................................. 7 ? pw ? output ? ode ............. ................................................................................................... 7 ? buzzer control ...................................................................................................................... 75 standard type tm C stm .......... .................................................................... 76 standard t ? operation ............. ............................................................................................ 76 standard t ? pe t ? register description ............................................................................... 77 standard t ? pe t ? operating ? odes .................................................................................... 81 compare output ? ode ............. ............................................................................................. 81 timer/counter ? ode ............................................................................................................. 84 pw ? output ? ode ............. ................................................................................................... 84 single pulse ? ode ................................................................................................................ 87 capture input ? ode .............................................................................................................. 87 capture timer module C captm .................................................................. 90 capture timer overview ....................................................................................................... 90 capture timer register description ..................................................................................... 90 capture timer operation ....................................................................................................... 94 capture ? ode operation ............. .......................................................................................... 94 compare ? ode operation ..................................................................................................... 94 noise filter ............................................................................................................................ 95 noise filter registers description ......................................................................................... 95 comparators .................................................................................................. 96 comparators block diagram ................................................................................................. 96 comparator operation .......................................................................................................... 97 analog to digital converter .......... ................................................................ 98 a/d overview ............. ........................................................................................................... 98 a/d converter register description ...................................................................................... 99 a/d converter data registers C adrl ? adrh ................................................................... 100 a/d converter control registers C adcr0 ? adcr1 ? adcr ?? addl ................................. 100 a/d converter boundar ? registers C adlvdl ? adlvdh ? adhvdl ? adhvdh ................. 10 ? a/d operation ..................................................................................................................... 10 ? summar ? of a/d conversion steps ............. ........................................................................ 104
rev. 1.00 4 ?a? 1?? ?01? rev. 1.00 5 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu programming considerations ............. ................................................................................. 105 a/d transfer function ............. ............................................................................................ 105 a/d programming examples ............................................................................................... 106 over-current detection ........... ..................................................................... 108 over-current functional description ................................................................................... 108 over-current register description ....................................................................................... 108 bldc motor control circuit ........... .............................................................. 110 functional description .......................................................................................................... 110 pw ? counter control circuit .............................................................................................. 111 ? ask function ...................................................................................................................... 115 other functions ................................................................................................................... 1 ? 0 hall sensor decoder ........................................................................................................... 1 ?? ? otor protection function ................................................................................................... 1 ? 0 i 2 c interface ................................................................................................. 135 i ? c interface operation ....................................................................................................... 1 ? 5 i ? c registers ....................................................................................................................... 1 ? 6 i ? c bus communication ..................................................................................................... 1 ? 9 i ? c bus start signal ............................................................................................................ 140 slave address .................................................................................................................... 140 i ? c bus read/write signal ................................................................................................. 140 i ? c bus slave address acknowledge signal ...................................................................... 141 i ? c bus data and acknowledge signal ............ .................................................................. 141 i ? c time-out control ............................................................................................................ 14 ? interrupts ...................................................................................................... 143 interrupt registers ............................................................................................................... 14 ? interrupt operation .............................................................................................................. 149 external interrupt 0 .............................................................................................................. 151 external interrupt 1 .............................................................................................................. 151 comparator interrupt ........................................................................................................... 151 time base interrupt ............................................................................................................. 151 ? ulti-function interrupt ........................................................................................................ 15 ? a/d converter interrupt ....................................................................................................... 15 ? pw ? ? odule interrupts ...................................................................................................... 15 ? capt ? ? odule interrupt .................................................................................................... 15 ? t ? interrupt ............. ............................................................................................................ 15 ? eepro ? interrupt ............. ................................................................................................. 154 lvd interrupt ....................................................................................................................... 154 i ? c interrupt ............. ............................................................................................................ 154 interrupt wake-up function ................................................................................................. 154 programming considerations ............. ................................................................................. 155 low voltage detector C lvd .......... ............................................................. 156 lvd register ............. .......................................................................................................... 156 lvd operation ..................................................................................................................... 157
rev. 1.00 6 ? a ? 1 ?? ? 01 ? rev. 1.00 7 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu application circuits ........... .......................................................................... 158 three phase bldc hall sensor solution (v b = ? 4v) ............. ............................................... 158 three phase bldc hall sensorless solution (v b = ? 4v) ..................................................... 158 single phase bldc hall sensor solution (v b =1 ? v) ........................................................... 159 single phase bldc hall sensorless solution (v b =1 ? v) ..................................................... 159 instruction set .............................................................................................. 160 introduction ......................................................................................................................... 160 instruction timing ................................................................................................................ 160 ? oving and transferring data ............................................................................................. 160 arithmetic operations .......................................................................................................... 160 logical and rotate operation ............................................................................................. 161 branches and control transfer ........................................................................................... 161 bit operations ..................................................................................................................... 161 table read operations ....................................................................................................... 161 other operations ............. .................................................................................................... 161 instruction set summar ? ..................................................................................................... 16 ? instruction defnition ................................................................................... 164 package information ................................................................................... 173 16-pin nsop (150mil) outline dimensions ......................................................................... 174 ? 0-pin ssop (150mil) outline dimensions ......................................................................... 175
rev. 1.00 6 ?a? 1?? ?01? rev. 1.00 7 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu features cpu features ? operating v oltage: f sys = 32khz ~ 20mhz: 4.5v~5.5v ? up to 0.2s instruction cycle with 20mhz system clock at v dd =5v ? power down and wake-up functions to reduce power consumption ? oscillators: internal 20mhz C hirc internal 32khz C lirc ? multi-mode operation: normal, slow, idle and sleep ? all instructions executed in one or two instruction cycles ? table read instructions ? 63 powerful instructions ? 6-level subroutine nesting ? bit manipulation instruction peripheral features ? flash program memory: 2k16 ? ram data memory: 2568 ? eeprom memory: 328 ? watchdog t imer function ? up to 18 bidirectional i/o lines ? four pin-shared external interrupts ? single 10-bit ctm ? single 16-bit ctm ? single 10-bit stm ? single 16-bit captm for motor protect ? 3-channel 10-bit pwm with comlementary outputs for bldc application ? 6-channel 10-bit resolution a/d converter ? time-base function for generation of fxed time interrupt signal ? single operational amplifer for current detect ion ? four comparators with interrupt functions ? single 8-bit d/a converter ? i 2 c interface ? low voltage reset function ? low voltage detect function ? package types: 16-pin nsop-a, 20-pin ssop-a
rev. 1.00 8 ? a ? 1 ?? ? 01 ? rev. 1.00 9 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu general description this device is flash memory with 8-bit high performance risc architecture microcontroller device which includes a host of fully integrated special features specifcally designed for the brushless dc motor applications. the advantages of low power consumption, i/o fexibility , multiple and extremely fexible t imer modules, o scillator o ptions, m ulti-channel a/ d a nd d/ a c onverter, pu lse w idth mo dulation function, 16-bit capture t imer module function, comparator functions, motor protect module, time ba se func tion, l vd, e eprom, powe r-down a nd wa ke-up func tions, com munication wi th the o utside wo rld i s c atered f or b y i ncluding f ully i ntegrated i 2c i nterface f unctions, a lthough especially designed for brushless dc motor applications, the enhanced versatility of this device also makes it applicab le for using in a wide range of a/d application possibilities such as sensor signal processing, motor driving, industrial control, consumer products, subsystem controllers, etc. block diagram vdd vss position detection ckt adc 10-bit x6 pa3/tck1/h1/c1p i 2 c pb0/hao/an3 pb3/tck0/c1n stm-10bit x1 ctm-10bit x1 ctm-16bitx1 pb1/ctin/hbo/an4 mcu (1)rom:2kw (2)ram:256x8 (3)eeprom:32x8 (4)stack:6 motor control ckt protection ckt current sense ckt pa1/tck2/an2/ap hirc=20mhz lirc=32khz wdt lvr lvd pc0/tp0_0/gat pc1/tp0_1/gab pc2/tp1_0/gbt pc3/tp1_1/gbb pc4/tp2_0/gct pc5/tp2_1/gcb avdd avss pa7/nfin/an1 pa2/scl/ocdsck/icpck pa0/sda/ocdsda/icpda pb2/hco/an5 pa4/h2/[sda]/c2p/[c1n] pa5/h3/[scl]/c3p pa6/[c1n]/an0
rev. 1.00 8 ?a? 1?? ?01? rev. 1.00 9 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu pin assignment pa 5/h?/[ scl ]/c?p pa 6/[ cin ]/ an 0 pa 7/ nfin / an 1 vss / avss vdd / avdd pa 1/ tck ?/ an ?/ ap pc 0/ tp 0_0/ gat pc 1/ tp 0_1/ gab pa 4/h?/[ sda ]/c?p/[c1n] pa ?/ tck 1/h1/c1p pa ?/ scl / ocdsck / icpck pa 0/ sda / ocdsda / icpda pc 5/ tp ?_1/ gcb pc 4/ tp ?_0/ gct pc ?/ tp 1_1/ gbb pc ?/ tp 1_0/ gbt ht 66 fm 5230 16 nsop -a 1 ? ? 4 5 6 7 8 16 15 14 1? 1? 11 10 9 ht 66 fm 5230 20 ssop -a 1 ? ? 4 5 6 7 8 9 ?0 19 18 17 16 15 14 1? 1? 11 10 pa 6/[ cin ]/ an 0 pa 7/ nfin / an 1 vss / avss vdd / avdd pa 1/ tck ?/ an ?/ ap pb 0/ hao / an ? pb 1/ ctin / hbo / an 4 pb ?/ hco / an 5 pc 0/ tp 0_0/ gat pc 1/ tp 0_1/ gab pa 5/h?/[ scl ]/c?p pa 4/h?/[ sda ]/c?p/[c1n] pa ?/ tck 1/h1/c1p pb ?/ tck 0/c1n pa ?/ scl / ocdsck / icpck pa 0/ sda / ocdsda / icpda pc 5/ tp ?_1/ gcb pc 4/ tp ?_0/ gct pc ?/ tp 1_1/ gbb pc ?/ tp 1_0/ gbt note: 1. if t he pi n-shared pi n funct ions have m ultiple outputs si multaneously, i ts pi n nam es a t t he right side of the "/" sign can be used for higher priority 2. vdd&a vdd means the vdd and a vdd are the double bonding. 3. vss&a vss means the vss and a vss are the double bonding.
rev. 1.00 10 ? a ? 1 ?? ? 01 ? rev. 1.00 11 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu pin descriptions pin name function op i/t o/t description pa0/sda/ ocdsda/icpda pa0 pawu papu st c ? os bidirectional 8-bit i/o port. register enabled pull-up and wake-up. sda paps0 st n ? os i ? c data ocdsda st c ? os on-chip debug support data/address pin icpda st c ? os in-circuit programming support data/address pin pa1/tck ? /an ? / ap pa1 papu pawu st c ? os bidirectional 8-bit i/o port. register enabled pull-up and wake-up. tck ? paps0 st t ? ? input an ? paps0 an a/d channel ? ap paps0 st operational amplifer input pa ? /scl/ ocdsck/icpck pa ? papu pawu st c ? os bidirectional 8-bit i/o port. register enabled pull-up and wake-up. scl paps0 st n ? os i ? c clock ocdsck st on-chip debug programming clock pin icpck st in-circuit programming clock pin pa ? /tck 1/h1/ c1p pa ? papu pawu st c ? os bidirectional 8-bit i/o port. register enabled pull-up and wake-up. tck1 paps0 st t ? 1 input h1 paps0 st hall sensor input c1p paps0 an comparator 1 input pa4/h ? / [sda]/ c ? p/ [c1n] pa4 papu pawu st c ? os bidirectional 8-bit i/o port. register enabled pull-up and wake-up. h ? paps1 st hall sensor input sda paps1 st n ? os i ? c data c ? p paps1 an comparator ? input c1n paps1 an comparator 1 input pa5/h ? / [scl]/ c ? p pa5 papu pawu st c ? os bidirectional 8-bit i/o port. register enabled pull-up and wake-up. h ? paps1 st hall sensor input scl paps1 st n ? os i ? c clock c ? p paps1 c ? os comparator ? input pa6 /[c1n]/an0 pa6 papu pawu st c ? os bidirectional 8-bit i/o port. register enabled pull-up and wake-up. c1n paps1 an comparator 1 input an0 paps1 an a/d channel 0 pa7/nfin/an1 pa7 papu pawu st c ? os bidirectional 8-bit i/o port. register enabled pull-up and wake-up. nfin paps1 st external interrupt 1 input an1 paps1 an a/d channel 1 pb0/hao/an ? pb0 pbpu st c ? os bidirectional 8-bit i/o port. register enabled pull-up. hao pbps0 c ? os test pin for sa an ? pbps0 an a/d channel ? pb1/ctin/hbo/ an4 pb1 pbpu st c ? os bidirectional 8-bit i/o port. register enabled pull-up. ctin pbps0 capt ? input hbo pbps0 c ? os test pin for sb an4 pbps0 an a/d channel 4
rev. 1.00 10 ?a? 1?? ?01? rev. 1.00 11 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu pin name function op i/t o/t description pb ? /hco/an5 pb ? pbpu st c ? os bidirectional 8-bit i/o port. register enabled pull-up. hco pbps0 c ? os test pin for s c an5 pbps0 an a/d channel 5 pb ? /tck 0/c1n pb ? pbpu st c ? os bidirectional 8-bit i/o port. register enabled pull-up. tck0 pbps0 st t ? 1 input c1n pbps0 st comparator 1 input pc0/tp0_0/gat pc0 pcpu st c ? os bidirectional 8-bit i/o port. register enabled pull-up. tp0_0 pcps0 st c ? os t ? 0 i/o gat pcps0 c ? os pulse width ? odulation complimentar ? output pc1/tp0_1/gab pc1 pcpu st c ? os bidirectional 8-bit i/o port. register enabled pull-up. tp0_1 pcps0 st c ? os t ? 0 i/o gab pcps0 c ? os pulse width ? odulation complimentar ? output pc ? /tp1_0/gbt pc ? pcpu st c ? os bidirectional 8-bit i/o port. register enabled pull-up. tp1_0 pcps0 st c ? os t ? 1 i/o gbt pcps0 c ? os pulse width ? odulation complimentar ? output pc ? /tp1_1/gbb pc ? pcpu st c ? os bidirectional 8-bit i/o port. register enabled pull-up. tp1_1 pcps0 st c ? os t ? 1 i/o gbb pcps0 c ? os pulse width ? odulation complimentar ? output pc4/tp ? _0/gct pc4 pcpu st c ? os bidirectional 8-bit i/o port. register enabled pull-up. tp ? _0 pcps1 st c ? os t ?? i/o gct pcps1 c ? os pulse width ? odulation complimentar ? output pc5/tp ? _1/gcb pc5 pcpu st c ? os bidirectional 8-bit i/o port. register enabled pull-up. tp ? _1 pcps1 st c ? os t ?? i/o gcb pcps1 c ? os pulse width ? odulation complimentar ? output vss vss pwr negative power suppl ?? ground avss avss pwr ground connection for a/d converter. the vss and avss are the same pin at package vdd vdd pwr positive power suppl ? avdd avdd pwr power suppl ? connection for a/d converter. the vdd and avdd are the same pin at package note : i/t: input type o/t: output type op: optional by confguration option (co) or register option pwr: power st: schmitt t rigger input cmos: cmos output; an: analog input pin vdd is the device power supply while a vdd is the adc power supply. vss is the device ground pin while a vss is the adc ground pin. as the pin description summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins.
rev. 1.00 1 ? ? a ? 1 ?? ? 01 ? rev. 1.00 1? ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu absolute maximum ratings supply v oltage .............. .................................................................................. v ss ?0.3v to v ss +6.0v input v oltage .............. .................................................................................... v ss ? 0.3v to v dd +0.3v storage t emperature ............... ..................................................................................... -50? c to 125?c operating t emperature .............. .................................................................................... -40? c to 85 ?c i oh t otal .............. ...................................................................................................................... -80ma i ol t otal .............. ....................................................................................................................... 80ma total power dissipation .............. .......................................................................................... 500mw note: t hese a re st ress ra tings onl y. st resses e xceeding t he ra nge spe cified und er "absol ute ma ximum ratings" m ay c ause su bstantial d amage t o t hese d evices. fu nctional o peration o f t hese d evices a t other c onditions be yond t hose l isted i n t he spe cifcation i s no t i mplied a nd pr olonged e xposure t o extreme conditions may affect devices reliability. d.c. characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage f sys = ?? ~ ? 0000khz 4.5 5.5 v i dd operating current (hirc osc) 5v no load ? f h = ? 0 ? hz ? adc off ? wdt enable ? ? otor_ctl off 9 1 ? ma i stb standb ? current lirc and lvr on ? lvd off ? wdt enable 60 100 v il input low voltage for i/o ports ? tckn ? h1 ? h ?? h ? and nfin 0 0. ? v dd v v ih input high voltage for i/o ports ? tckn ? h1 ? h ?? h ? and nfin 0.7v dd v dd v v lvr lvr voltage level lvr enable ? ? .15v option -5% ? .15 +5% v v lvd lvd voltage level lvden=1 ? v lvd = ? .6v -5% ? .6 +5% v v ol output low voltage for i/o ports 5v i ol = ? 0ma 0.5 v v oh output high voltage for i/o ports 5v i oh =-7.4ma 4.5 v r ph pull-high resistance for i/o ports 5v 10 ? 0 50 n
rev. 1.00 1? ?a? 1?? ?01? rev. 1.00 1 ? ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu a.c. characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions f sys s ? stem clock 4.5v~5.5v ?? ? 0000 khz f hirc s ? stem clock (hirc) 4.5v~5.5v ta=-40?c~85?c -1 ? % ? 0 +4% ? hz ta=-20?c~85?c -9% ? 0 +4% ? hz ta=25?c - ? % ? 0 + ? % ? hz f ti ? er timer input pin frequenc ? 4 f sys t int interrupt pulse width 1 t sys t lvr low voltage width to reset 1 ? 0 ? 40 480 s t lvd low voltage width to interrupt ? 0 45 90 s t lvds lvdo stable time 15 s t eerd eepro ? read time 45 90 s t eewr eepro ? write time ? 4 ms t sst s ? stem start-up timer period (wake-up from halt) f sys =hirc 15~16 t sys t rstd s ? stem reset dela ? time (power on reset) ? 5 50 100 ms s ? stem reset dela ? time (an ? reset except power on reset) 8. ? 16.7 ?? . ? ms 1rwh w sys i sys 7 pdd dffudf i ud fdu iutf d ) gfs fdsdfu g ffg dg 66 dg fdg d f gyf d s hirc frequency accuracy over device v dd and temperature - 1? %~+4% 85 70 25 0 - 40 4.5 | 5. 5 ?% -9%~+4% temperature ( ) v dd (v) - 20 -9%~+4% +-?%
rev. 1.00 14 ? a ? 1 ?? ? 01 ? rev. 1.00 15 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu a/d converter characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd condition av dd a/d converter operating voltage v lvr 5.0 5.5 v i op a/d converter operating current ? v 0.8 ma 5v 1 ma i stby adc standb ? current digital input no change 1 a v ref a/d converter reference voltage ? av dd av dd +0.1 v t conv a/d conversion time 14 t adck dnl a/d differential non-linearit ? 4.5v v ref =av dd =v dd ? t ad =0.2s - ? ? lsb 5.5v v ref =av dd =v dd ? t ad =0.2s 4.5v v ref =av dd =v dd ? t ad =6.4s 5.5v v ref =av dd =v dd ? t ad =6.4s 4.5v v ref =av dd =v dd ? t ad =12.8s 5.5v v ref =av dd =v dd ? t ad =12.8s inl a/d integral non-linearit ? 4.5v v ref =av dd =v dd ? t ad =0.2s -4 4 lsb 5.5v v ref =av dd =v dd ? t ad =0.2s 4.5v v ref =av dd =v dd ? t ad =6.4s 5.5v v ref =av dd =v dd ? t ad =6.4s 4.5v v ref =av dd =v dd ? t ad =12.8s 5.5v v ref =av dd =v dd ? t ad =12.8s g err gain error ? lsb t adck adclk period 0.166 s t ckh adclk high width 8 ? ns t ckl adclk low width 8 ? ns t st1 setup time for adon ? ns t st ? setup time for start latch ? ns t sth start high width ? 5 ns t deoc eocb output dela ? av dd =5v ? ns t dout output dela ? av dd =5v ? ns t on adc wake up time ? s t off adc sleep time 5 ns d/a converter characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions v dd d/a operating current v lvr 5.5 v v da d/a output voltage 00h ~ ffh ? no load 0.01 0.99 v dd t dac d/a conversion time v dd =5v ? c l =10pf ? s r o d/a output resistance 10 k
rev. 1.00 14 ?a? 1?? ?01? rev. 1.00 15 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu 8-bit r-2r d/a converter (analog conditon v dd =5v, c l =10pf) model corner tt sf fs ss ff temperature 25?c 25?c 25?c 90?c -40?c operating average current (v dd =5v ? c l =10pf) 352a 330a 374a 297a 413a analog output 00000000 (b) ~11111111 (b) 0~4.98v 0~4.981v 0~4.98v 0~4.98v 0~4.981v conversion time 2s 2s 2s 2s 2s operational amplifer characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions v opr1 operating voltage ? . ? v ? .7 ? . ? 5.5 v i off1 power down current ? . ? v 0.1 a v opos1 input offset voltage ? . ? v without calibration ? aof[ 4:0]=10000b -15 +15 mv v opos ? input offset voltage ? . ? v b ? calibration - ? + ? mv v c ? common ? ode voltage range ? . ? v v ss v dd - 1.4v v psrr power suppl ? rejection ratio ? . ? v 90 96 db c ? rr common ? ode rejuction ratio ? . ? v v c ? =0~v dd -1.4v 106 db sr slew rate+ ? slew rate- ? . ? v r l =600, c l =100pf 1. ? 9 ? .18 ? .5 v/s gbw gain band width ? . ? v r l =600, c l =100pf ? .05 ? .70 7.16 ? hz a ol open loop gain ? . ? v r l =600, c l =100pf 96 db p ? phase ? argin ? . ? v r l =600, c l =100pf 90 symbol parameter test conditions min. typ. max. unit v dd conditions v opr1 operating voltage 5v ? .7 ? . ? 5.5 v i off1 power down current 5v 0.1 a v opos1 input offset voltage 5v without calibration ? aof[ 4:0]=10000b -15 +15 mv v opos ? input offset voltage 5v b ? calibration - ? + ? mv v c ? common ? ode voltage range 5v v ss v dd - 1.4v v psrr power suppl ? rejection ratio 5v tbd tbd tbd db c ? rr common ? ode rejuction ratio 5v v c ? =0 ~ v dd -1.4v tbd tbd tbd db sr slew rate+ ? slew rate- 5v r l =600, c l =100pf tbd tbd tbd v/s gbw gain band width 5v r l =600, c l =100pf tbd tbd tbd ? hz a ol open loop gain 5v r l =600, c l =100pf tbd tbd tbd db p ? phase ? argin 5v r l =600, c l =100pf tbd tbd tbd
rev. 1.00 16 ? a ? 1 ?? ? 01 ? rev. 1.00 17 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu comparator electrical characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd condition v c ? p comparator operating voltage 5v ? . ? 5.0 5.5 v i c ? p comparator operatiing current 5v ? 00 450 a i off comparator power down current 5v comparator disable 0.1 a v c ? pos comparator input offset voltage 5v -10 +10 mv v hys0 h ? steresis width 5v comparator 0 tbc 100 tbc mv v hys1 h ? steresis width 5v comparator 1 ???? ? 0 40 60 mv v c ? input common ? ode voltage range v ss v dd -1.4 v a ol comparator open loop gain 100 1 ? 0 db t pd1 comparator response time 5v v ? = 0~(v dd -1.4)v with 10mv overdrive 1 s t pd ? comparator response time 5v *with 100mv overdrive (note) ? 00 ns 1rwh 0hdvxuhg zlwk frpsdudwru rqh lqsxw slq dw 9 0 9 dd u s s ud iup 66 p u iup dd p power on reset electrical characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd condition v por v dd start voltage to ensure power-on reset 100 mv rr vdd v dd rise rate to ensure power-on reset 0.0 ? 5 v/ms t por ? inimum time for v dd to remain at v por to ensure power-on reset 1 ms             
rev. 1.00 16 ?a? 1?? ?01? rev. 1.00 17 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu system architecture a key factor in the high-performan ce features of the holtek range of microcontrollers is attributed to their internal system architecture . the device takes advantage of the usual features found within risc microcontrollers providing increased speed of operation and periodic performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or c all i nstructions. an 8-bi t wi de al u i s use d i n pra ctically a ll i nstruction se t ope rations, whi ch carries out arithme tic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplified by moving data through the accumulator and the alu. certain internal regis ters are implemented in the d ata m emory and can be directly or indirectly addressed. the simpl e addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d c ontrol system with m aximum reliability a nd fexibility. t his makes t he device suitable for l ow- cost, high-volume production for controller applications. clocking and pipelining the m ain syst em c lock, de rived from e ither a n hirc or l irc osc illator i s subdi vided i nto four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way , one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructio ns takes place in consecutive instruction c ycles, t he pi pelining st ructure of t he m icrocontroller e nsures t hat i nstructions a re effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute.                                                       
              ?                ?      ? ? ? ? ? ? system clock and pipelining
rev. 1.00 18 ? a ? 1 ?? ? 01 ? rev. 1.00 19 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle t o frst obt ain t he a ctual j ump or c all a ddress a nd t hen a nother c ycle t o a ctually e xecute t he branch. the requirement for this extra cycle should be taken into accou nt by programmers in timing sensitive applications.                             
      ? ? ? ?     ?  ? ? ?   ?                               ? instruction fetching program counter during pro gram e xecution, t he progr am co unter i s use d t o ke ep t rack of t he a ddress of t he next instruction to be executed. it is automatically incremented by one each time an instruction is e xecuted e xcept for i nstructions, suc h a s "jmp" or "cal l" t hat de mand a j ump t o a non- consecutive program memory address. only the lower 8 bits, known as the program counter low register, are directly addressable by the application program. when executi ng instructions re quiring jumps to non-consecutive addresses suc h as a jump instruction, a subrout ine c all, i nterrupt or re set, e tc., t he m icrocontroller m anages progra m c ontrol by loading the required address into the program counter . for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execut ion, is discarded and a dummy cycle takes its place while the correct instruction is obtained. program counter program counter high byte pcl register pc10~pc8 pcl7~pcl0 the lower byte of the program counter , known as the program counter low register or pcl, is available for program control and is a readable and writeable register . by transferring data directly into t his r egister, a sh ort p rogram j ump c an b e e xecuted d irectly, h owever, a s o nly t his l ow b yte is available for manipulation, the jum ps are limited to the present page of memory , that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch.
rev. 1.00 18 ?a? 1?? ?01? rev. 1.00 19 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer , and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allowing the programmer to use the structure more easily . however , when the stack is full, a call subroutine instruction can still be exec uted whic h wi ll result in a st ack overfow . prec autions should be ta ken to avoid such cases which might cause unpredictable program branching. if the stack is overfow , the frst program counter save in the stack will be lost.                                
                          arithmetic and logic unit C alu the arith metic-logic unit or alu is a critical area of the microcontrol ler that carries out arithmetic and logic operations of the instructi on set. connected to the main micro controller data bus, the alu receives related ins truction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register . as these alu calculation or operations may result in carry , borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla ? rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc ? increment and decrement inca, inc, deca, dec ? branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti
rev. 1.00 ? 0 ? a ? 1 ?? ? 01 ? rev. 1.00 ?1 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu flash program memory the program memory is the locatio n where the user code or program is stored. for this device the program memory is flash type, which means it can be programmed and re-programmed a lar ge number o f t imes, a llowing t he u ser t he c onvenience o f c ode m odification o n t he sa me d evice. by using the appropriate programming tools, this flash device of fers users the flexibility to conveniently debug and develop their applications while also of fering a means of feld programming and updating. structure the progra m me mory ha s a c apacity of 2k16 bi ts. t he progra m me mory i s a ddressed by t he program counter and also contains data, table information and interrupt entries. t able data, which can be setup in any location within the program memory , is addressed by a separate table pointer register. special vectors within the program memory , certai n locations are reserved for the reset and interrupts. the location 000h is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution.             
     program memory structure look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. t o use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register , tblp and tbhp . these registers defne the total address of the look-up table. after se tting u p t he t able p ointer, t he t able d ata c an b e r etrieved f rom t he pr ogram me mory u sing the " tabrdc[m]" or " tabrdl[m]" instructions , respectively . when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defined data me mory r egister [ m] a s sp ecified i n t he i nstruction. t he h igher o rder t able d ata b yte f rom the program memory will be transferred to the tblh special register . any unused bits in this transferred higher order byte will be read as "0". the accompanying diagram illustrates the addressing data fow of the look-up table.                            
                            
   
rev. 1.00 ?0 ?a? 1?? ?01? rev. 1.00 ? 1 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu instruction table location bits b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 tabrd c [m] @10 @9 @8 @7 @6 @5 @4 @ ? @ ? @1 @0 tabrdl [m] 1 1 1 @7 @6 @5 @4 @ ? @ ? @1 @0 table location note: b10~b0: t able location bits @7~@0: t able pointer (tblp) bits @10~@8: t able pointer (tbhp) bits table program example the fol lowing exam ple shows how t he t able poi nter and t able data i s defned and retrie ved from t he microcontroller. this example uses raw table data located in the program memory which is stored there using the org statement. the value at this org statement is "700h" which refers to the start address of the last page within the 2k words program memory of the device. the table pointer is setup here to have an initial value of "06h". this will ensure that the frst data read from the data table will be at the program memory address "706h" or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the present page if the "t abrdc [m]" instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the "tabrdc [m]" instruction is executed. because the tblh register is a read-only register and cannot be res tored, care should be taken to ensure its protection if both the main routine and interrupt s ervice routine us e table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however , in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. table read program example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address is referenced mov tblp,a mov a,07h ; initialise high table pointer mov tbhp,a : : tabrdc tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address "706h" transferred to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrdc tempreg2 ; transfers value in table referenced by table pointer data at program ; memory address "705h" transferred to tempreg2 and tblh in this ; example the data "1ah" is transferred to tempreg1 and data "0fh" to ; register tempreg2 : : org 700h ; sets initial address of program memory dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : :
rev. 1.00 ?? ? a ? 1 ?? ? 01 ? rev. 1.00 ?? ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu in circuit programming the provision of flash type program memory provides the user with a means of convenient and easy upgrades a nd m odifcations t o t heir p rograms o n t he sa me d evice. as a n a dditional c onvenience, holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller , and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. the holtek flash mcu to w riter programming pin correspondence table is as follows: holtek write pins mcu programming pins function icpda pa0 programming serial data/address icpck pa ? programming serial clock vdd vdd power suppl ? vss vss ground during the programming process, the user must there take care to ensure that no other outputs are c onnected t o t hese t wo pi ns.the pro gram me mory a nd e eprom da ta m emory c an bo th be programmed serially in-circuit using this 4-wire interface. data is downloaded and uploaded serially on a single pin with an additional line for the clock. t wo additional lines are required for the power supply. the technical details regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature.                        
                        note: * may be resistor or capacitor. the resistance of * must be greater than 1k or the capacitance of * must be less than 1nf.
rev. 1.00 ?? ?a? 1?? ?01? rev. 1.00 ?? ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu on-chip debug support C ocds an ev chip exists for the purposes of device emulation. this ev chip device also provides an "on-chip d ebug" function to debug the device during the development process . the ev chip and the actual mcu devices are almos t functionally compatible except for the " on-chip debug" function. users can use the ev chip device to emulate the real chip device behavior by connecting the ocdsda and ocdsck pins to the holtek ht -ide development tools. the ocdsda pin is the ocds data/address input/output pin while the ocdsck pin is the ocds clock input pin. when users use the ev chip for debugging, other functions which are shared with the ocdsda and ocdsck pins in the actual mcu device will have no ef fect in the ev chip. however , the two ocds pins which are pin-shared with the icp programming pins are still used as the flash memory programming pins for icp . for a more detailed ocds description, refer to the corresponding document named "holtek e-link for 8-bit mcu ocds users guide". holtek e-link pins ev chip pins pin description ocdsda ocdsda on-chip debug support data/address input/output ocdsck ocdsck on-chip debug support clock input vdd vdd power suppl ? gnd vss ground ram data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. the ram data memory capacity is up to 256 8 bits. structure divided into two sections, the frst of these is an area of ram, known as the special function data memory. he re a re l ocated r egisters wh ich a re n ecessary f or c orrect o peration o f t he d evice. ma ny of these registers can be read from and written to directly under program control, however , some remain protected from user manipulation. the second area of data memory is known as the general purpose data memory , which is reserved for general purpose use. all locations within this area are read and write accessible under program control. the overall data memory is subdivided into two banks. the special purpose data memory registers are accessible in all banks, with the exception of the eec register at address 40h, which is only accessible in bank 1. switching between the dif ferent data memory banks is achieved by setting the bank pointer to the correct value. the start address of the data memory for the device is the address 00h.                         
 
     data memory structure
rev. 1.00 ? 4 ? a ? 1 ?? ? 01 ? rev. 1.00 ?5 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu                                                                                                                                                                                                                                                                                     


       
 
                                        
                        
 
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rev. 1.00 ?4 ?a? 1?? ?01? rev. 1.00 ? 5 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu special function register description most of the special function register details will be described in the relevant functional section, however several registers require a separate description in this section. indirect addressing registers C iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0 and iar1 registers will result in no actual read or write operatio n to these registers but rather to the memory location specifed by their corresponding memory pointers, mp0 or mp1. acting as a pair, iar0 and mp0 can together access data from bank 0 while the iar1 and mp1 register pair can access data from any bank. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of "00h" and writing to the registers indirectly will result in no operation. memory pointers C mp0, mp1 two me mory po inters, k nown a s mp0 a nd mp1 a re p rovided. t hese me mory po inters a re physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the releva nt indirect addressing registers is carried out, the actual address that the microcontroller is di rected to is the address specifed by the relat ed memory pointer . mp0, together with indirect addressing register , iar0, are used to access data from bank 0, while mp1 and iar1 are used to access data from all banks according t o bp register. direct ad dressing c an only be used with bank 0, all other banks must be addressed indirectly using mp1 and iar1. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. indirect addressing program example data .section data adres1 d b ? adres2 d b ? adres3 d b ? adres4 d b ? block d b ? code .section at 0 code org00h start : m ov a , 04h ; setup size of block m ov block , a m ov a , offset adres1 ; accumulator loaded with frst ram address m ov mp0 , a ; setup memory pointer with frst ram address loop : c lr iar0 ; clear the data at address defned by mp0 i nc mp0 ; increment memory pointer s dz block ; check if last memory location has been cleared jm p loop continue : the important point to note here is that in the example shown above, no reference is made to specifc data memory addresses.
rev. 1.00 ? 6 ? a ? 1 ?? ? 01 ? rev. 1.00 ?7 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu bank pointer C bp for this device, the data memory is divided into two banks, bank0 and bank1. selecting the required data memory area is achieved using the bank pointer . bit 0 of the bank pointer is used to select data memory banks 0~1. the data memory is initialised to bank 0 after a reset, except for a wd t time-out reset in the power down mode, in which case, the data memory bank remains unaf fected. it should be noted that the special function data memory is not af fected by the bank selection, which means that the special function regi sters ca n be ac cessed from wi thin any bank. di rectly addressi ng the da ta me mory will always result in bank 0 being accessed irrespective of the value of the bank pointer . accessing data from bank1 must be implemented using indirect addressing. bp register bit 7 6 5 4 3 2 1 0 name d ? bp0 r/w r/w por 0 bit 7 ~ 1 unimplemented, read as "0" bit 0 dmbp0: select data memory banks 0: bank 0 1: bank 1 accumulator C acc the a ccumulator is central to the operation of any microcontroller and is clos ely related w ith operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. w ithout the accumulator it would be necessary to write the result of each c alculation or l ogical ope ration suc h a s a ddition, subt raction, shi ft, e tc., t o t he da ta me mory resulting i n highe r program ming and t iming overheads. da ta t ransfer operat ions usual ly i nvolve the t emporary st orage func tion of t he ac cumulator; for e xample, wh en t ransferring da ta be tween one user -defined register and another , it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory . by manipulating this register , direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers C tblp, tbhp, tblh these three special function registers are used to cont rol operation of the look-up table which is stored i n t he progra m me mory. t blp a nd t bhp a re t he t able poi nters a nd i ndicate t he l ocation where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the "inc" or "dec" instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored afte r a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location.
rev. 1.00 ?6 ?a? 1?? ?01? rev. 1.00 ? 7 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu status register C status this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (t o). these arithmetic/logical operation and system management fags are used to record the status and operation of the microcontroller. with the exceptio n of the t o and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the t o or pdf fag. in addition, operations related to the status register may give dif ferent results due to the dif ferent instruction operati ons. the t o fag can be af fected only by a system power -up, a wdt time-out or by executing the "clr wdt" or "hal t" instruction. the pdf fag is af fected only by executing the "halt" or "clr wdt" instruction or during a system power-up. the z, ov, ac and c fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also af fected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. ? pdf is cleared by a system power -up or executing the "clr wdt" instruction. pdf is set by executing the "halt" instruction. ? to is cle ared by a system power -up or executing the "clr wdt" or "hal t" instruction. t o is set by a wdt time-out. in additio n, on entering an interrup t sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically . if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it.
rev. 1.00 ? 8 ? a ? 1 ?? ? 01 ? rev. 1.00 ?9 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu status register bit 7 6 5 4 3 2 1 0 name to pdf ov z ac c r/w r r r/w r/w r/w r/w por 0 0 "" unknown bit 7 ~ 6 unimplemented, read as "0" bit 5 to: w atchdog t ime-out fag 0: after power up or executing the "clr wdt" or "halt" instruction 1: a watchdog time-out occurred. bit 4 pdf: power down fag 0: after power up or executing the "clr wdt" instruction 1: by executing the "halt" instruction bit 3 ov: overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z: zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac: auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c: carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction.
rev. 1.00 ?8 ?a? 1?? ?01? rev. 1.00 ? 9 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu eeprom data memory one of the s pecial features in the device is its internal eep rom d ata m emory. eep rom, w hich stands for electrically erasable programmable read only memory , is by its nature a non-volatile form of memory , with data retention even when its power supply is removed. by incorporating this kind of data mem ory, a whol e new host of appl ication possibi lities are ma de avail able to the designer. the availability of eeprom storage allows information such as product identification numbers, calibration values, specifc user data, system setup data or other product information to be stored directly within the product microcontroller . the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. eeprom data memory structure the eeprom data memory capacity is up to 328 bits. unlike the program memory and ram data memory , the eeprom data memory is not directly mapped and is therefore not directly accessible in the same way as the other types of memory . read and w rite operations to the eeprom are carried out in single byte operations using an address and data register in bank 0 and a single control register in bank 1. eeprom registers three registers control the overall operation of the internal eeprom data memory . these are the address register , eea, the data register , eed and a single control register , eec. as both the eea and eed registers are located in bank 0, they can be directly accessed in the same way as any other special functi on regist er. the eec register however , be ing located in bank1, cannot be direct ly addressed directly and can only be read from or written to indirectly using the mp1 memory pointer and indirect addressing register , iar1. because the eec control register is located at address 40h in bank 1, the mp1 memory pointer must frst be set to the value 40h and the bank pointer register , bp, set to the value, 01h, before any operations on the eec register are executed. eeprom control registers list name bit 7 6 5 4 3 2 1 0 eea d4 d ? d ? d1 d0 eed d7 d6 d5 d4 d ? d ? d1 d0 eec wren wr rden rd eea register bit 7 6 5 4 3 2 1 0 name d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 ~ 5 unimplemented, read as "0" bit 4 ~ 0 data eeprom address data eeprom address bit 4 ~ bit 0
rev. 1.00 ? 0 ? a ? 1 ?? ? 01 ? rev. 1.00 ?1 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu eed register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 0 data eeprom data data eeprom data bit 7 ~ bit 0 eec register bit 7 6 5 4 3 2 1 0 name wren wr rden rd r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 ~ 4 unimplemented, read as "0" bit 3 wren: data eeprom w rite enable 0: disable 1: enable this is the d ata eep rom w rite enable bit w hich mus t be s et high before d ata eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. bit 2 wr: eeprom w rite control 0: w rite cycle has fnished 1: activate a write cycle this i s t he da ta e eprom w rite c ontrol b it a nd wh en se t h igh b y t he a pplication program will activ ate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has fnished. setting this bit high will have no ef fect if the wren has not frst been set high. bit 1 rden: data eeprom read enable 0: disable 1: enable this is the data eeprom read enable bit which must be set high before data eeprom read operations are carried out. clearing this bit to zero w ill inhibit d ata eeprom read operations. bit 0 rd: eeprom read control 0: read cycle has fnished 1: activate a read cycle this is the data eeprom read control bit and when set high by the applic ation program will activ ate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no ef fect if the rden has not frst been set high. note: the wren, wr, rden and rd can not be set to "1" at the same time in one instruction. the wr and rd can not be set to "1" at the same time.
rev. 1.00 ?0 ?a? 1?? ?01? rev. 1.00 ? 1 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu reading data from the eeprom to read data from the eep rom, the read enable bit, rden , in the eec register must frs t be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eea register . if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle term inates, the rd bit will be automatically cleared to zero, after which the data can be read from the eed register . the data will remain in the eed register until another read or write operation i s e xecuted. t he a pplication pr ogram c an po ll t he rd bi t t o de termine whe n t he da ta i s valid for reading. writing data to the eeprom to wr ite da ta t o t he e eprom, t he wr ite e nable bi t, w ren, i n t he e ec re gister m ust frst be se t high to enable the w rite function. the eep rom addres s of the data to be w ritten mus t then be placed in the eea register and the data placed in the eed register . if the wr bit in the eec register is now set high, an internal write cycle will then be initiated. setting the wr bit high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has fni shed c an be i mplemented e ither by pol ling t he w r bi t i n t he e ec re gister or by usi ng t he eeprom i nterrupt. w hen t he wr ite c ycle t erminates, t he w r b it wi ll b e a utomatically c leared t o zero by the microcontroller , informing the user that the data has been written to the eeprom. the application program can therefore poll the wr bit to determine when the write cycle has ended. write protection protection against inadvertent write operation is provided in several ways. after the device is powered- on t he w rite ena ble bit i n t he control regist er wi ll be cl eared pre venting any writ e opera tions. al so at power -on the bank pointer , bp , will be reset to zero, which means that data memory bank 0 will be selected. as the eeprom control register is located in bank 1, this adds a further measure of protection against spurious write operations. during normal program operation, ensuring that the w rite enable bit in the control register is cleared will safeguard against incorrect write operations. eeprom interrupt the eeprom write interrupt is generated when an eeprom write cycle has ended. the eeprom interrupt must frst be enabled by setting the epwe bit in the relevant interrupt register . when an eeprom write cycle ends, the epwf request fag will be set. if the globa l and eeprom interrupts are enabled and the stack is not full, a jump to the associated interrupt vector will take place. when the interrupt is serviced, the eeprom interrupt fag will be automatica lly reset. more details can be obtained in the interrupt section. programming considerations care must be taken that data is not inadvertently written to the eeprom. protection can be periodic by ensuring that the w rite enable bit is normally cleared to zero when not writing. also the bank pointer could be normally cleared to zero as this would inhibit access to bank 1 where the eeprom control register exist. although certainly not necessary , consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. when writing data the wr bit must be set high immediately after the wren bit has been set high, to ensure the write cycle executes correctly . the global interrupt bit emi should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts.
rev. 1.00 ?? ? a ? 1 ?? ? 01 ? rev. 1.00 ?? ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu programming examples reading data from the eeprom - polling method mov a, eeprom_adres ; user defned address mov eea, a mov a, 040h ; setup memory pointer mp1 mov mp1, a ; mp1 points to eec register mov a, 01h ; setup bank pointer mov bp, a set iar1.1 ; set rden bit, enable read operations set iar1.0 ; start read cycle - set rd bit back: sz iar1.0 ; check for read cycle end jmp back clr iar1 ; disable eeprom write clr bp mov a, eed ; move read data to register mov read_data, a writing data to the eeprom - polling method clr emi mov a, eeprom_adres ; user defned address mov eea, a mov a, eeprom_data ; user defned data mov eed, a mov a, 040h ; setup memory pointer mp1 mov mp1, a ; mp1 points to eec register mov a, 01h ; setup bank pointer mov bp, a set iar1.3 ; set wren bit, enable write operations set iar1.2 ; start write cycle - set wr bit set emi back: sz iar1.2 ; check for write cycle end jmp back clr iar1 ; disable eeprom write clr bp
rev. 1.00 ?? ?a? 1?? ?01? rev. 1.00 ?? ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu oscillator various oscillator options of fer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through registers. oscillator overview in additio n to being the source of the main system clock the oscillators also provide clock sources for the w atchdog t imer and t ime base interrupts. fully integrated inte rnal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. the h igher f requency o scillators p rovide h igher p erformance b ut c arry wi th i t t he d isadvantage o f higher power requirements, while the opposite is of course true for the lower frequency oscillators. with the capabilit y of dynamically switching between fast and slow system clock, the device has the fexibility to optim ize the performance/power ratio, a feature especially important in power sensitive portable applications. type name freq. internal high speed rc hirc ? 0 ? hz internal low speed rc lirc ?? khz oscillator types system clock confgurations there are t wo m ethods of generat ing t he syst em cl ock, a high spee d osci llator and a l ow spee d oscillator. the high speed oscillator is the internal 20mhz rc oscillator . the low speed oscillator is t he i nternal 32 khz (l irc) osc illator. se lecting whe ther t he l ow or hi gh spe ed o scillator i s use d as the system oscillator is implemented using the hlclk bit and cks2 ~ cks0 bits in the smod register and as the system clock can be dynamically selected. the actua l source clock used for the high speed and the low speed oscillators is chosen via registers. the frequency of the slow speed or high speed system clock is also determined using the hlclk bit and cks2 ~ cks0 bits in the smod register . note that two oscillator selections must be made namely one high speed and one low speed system oscillators. it is not possible to choose a no- oscillator selection for either the high or low speed oscillator.
rev. 1.00 ? 4 ? a ? 1 ?? ? 01 ? rev. 1.00 ?5 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu             
                            ?   ?  ? ? ?  ??  ?  - ? ??  system clock confgurations internal 20mhz rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc oscillator has a fixed frequency of 20mhz. device trimming during the manufacturing process and the inclusion of internal frequency compensati on circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of 5v and at a temperature of 25?c degrees, the fxed oscillation frequency of 20mhz will have a tolerance within 2%. internal 32khz oscillator C lirc the internal 32khz system oscillator is a low frequency oscillator choice. it is a fully integrated rc osc illator wi th a t ypical fre quency of 32khz a t 5v , re quiring no e xternal c omponents for i ts implementation. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of 5v and at a tempe rature of 25?c degrees, the fxed oscillation frequency of 32khz will have a tolerance within 10%. supplementary clocks the low speed oscillator , in addition to providing a system clock source are also used to provide a clock source to other device functions. these are the w atchdog t imer and the t ime base interrupt.
rev. 1.00 ?4 ?a? 1?? ?01? rev. 1.00 ? 5 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu operating modes and system clocks present day appl ications require that their mi crocontrollers have high performance but often sti ll demand that they consume as little power as possible, conficting requirements that are especially true i n ba ttery powe red por table a pplications. t he fa st c locks re quired for hi gh pe rformance wi ll by t heir na ture i ncrease c urrent c onsumption a nd of c ourse vi ce-versa, l ower spe ed c locks re duce current consumption. as holtek has provided this device with both high and low speed clock sources and the means to switch between them dynamically , the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clocks the device has many dif ferent clock sources for both the cpu and peripheral function operation. by providing the us er w ith a w ide range of clock options us ing conf guration options and regis ter programming, a clock system can be confgured to obtain maximum application performance. the m ain sy stem c lock, c an c ome f rom e ither a h igh f requency, f h , o r l ow f requency, f l , so urce, and is selected using the hlclk bit and cks2~cks0 bits in the smod register . the high speed system clock can be sourced from the hirc oscillator . the low speed system clock source can be sourced from t he l irc osc illator. t he ot her c hoice, wh ich i s a di vided ve rsion of t he hi gh spe ed system oscillator has a range of f h /2~f h /64. there are two additional internal clocks for the peripheral circuits, the substitute clock, f sub , and the time base clock, f tbc . each of these internal clocks is sourced by the lirc oscillator.                                
                ?    ?  ??             ??  - ?  ? ?    ?? ? ? ? ?  ? ? ?    ?? system clock confgurations note: when the system clock source f sys is switched to f l from f h , the high speed oscillation will stop to conserve the power. thus there is no f h ~f h /64 for peripheral circuit to use.
rev. 1.00 ? 6 ? a ? 1 ?? ? 01 ? rev. 1.00 ?7 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu system operation modes there a re f ive d ifferent m odes o f o peration f or t he m icrocontroller, e ach o ne wi th i ts o wn special characteristics and which can be chosen according to the specific performance and power requirements of the appl ication. there are two modes all owing normal operati on of the microcontroller, the normal mode and slow mode. the remaining three modes, the sleep , idle0 and idle1 mode are used when the microcontroller cpu is switched off to conserve power. operating mode description cpu f sys f sub f s f tbc nor ? al mode on f h ~f h /64 on on on slow mode on f l on on on idle0 mode off off on on on idle1 mode off on on on on sleep mode off off on on off normal mode as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by the high speed oscillator . this mode operates allo wing the microco ntroller to operate normally with a clock source will come from the high speed oscillator , hirc. the high speed oscillator will however frst be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the cks2~cks0 and hlclk bits in the smod regis ter. a lthough a high s peed os cillator is us ed, running the microcontroller at a divided clock ratio reduces the operating current. slow mode this is also a mode where the microcontroller operates normally altho ugh now with a slower speed clock source. the clock source used will be from f l . running the microcontroller in this mode allows it to run with much lower operating currents. in the slow mode, the f h is off. sleep mode the sleep mode is entered when an hal t instruction is executed and when the idlen bit in the smod re gister i s l ow. in t he sl eep m ode t he cpu wi ll be st opped. howe ver t he f l c locks wi ll continue to operate. idle0 mode the idle0 mode is entered when a hal t instruction is executed and when the idlen bit in the smod regi ster i s high and t he fsyson bit i n t he ctrl regi ster i s l ow. in t he idle 0 mode t he system oscillator will be inhibited from driving the cpu but some peripheral functions will remain operational such as the w atchdog t imer, tm s and iic. in the idle0 mode the system oscillator will be stopped , the w atchdog t imer clock, f s , will be on. idle1 mode the idle1 mode is entered when a hal t instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the ctrl register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu but may continue to provide a clock source to keep some peripheral functions operational such as the w atchdog t imer and tms. in the idle1 mode the system oscillator will continue to run, and this system oscilla tor may be high speed or low speed system oscillator. in the idle1 mode the low frequency clock f s will be on.
rev. 1.00 ?6 ?a? 1?? ?01? rev. 1.00 ? 7 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu control register the smod register is used to control the internal clocks within the device. smod register bit 7 6 5 4 3 2 1 0 name cks ? cks1 cks0 lto hto idlen hlclk r/w r/w r/w r/w r r r/w r/w por 0 0 0 0 0 1 1 bit 7 ~ 5 cks2 ~ cks0 : the system clock selection when hlclk is "0" 000: f l lirc 001: f l lirc ) 010: f h /64 011: f h /32 100: f h /16 101: f h /8 110: f h /4 111: f h /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which can be lirc, a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 unimplemented, read as "0". bit 3 lto: lirc system osc sst ready fag 0: not ready 1: ready this is the low speed system oscillator sst ready fag which indicate s when the low speed system oscillator is stable after power on reset or a wake-up has occurred. the fag will change to a high level after 1~2 cycles if the lirc oscillator is used. bit 2 hto: hirc system osc sst ready fag 0: not ready 1: ready this is the high speed system oscill ator sst ready fag which indicates when the high speed system oscillator is stable after a wake-up has occurred. this fag is cleared to "0" by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. therefore this fag will always be read as "1" by the application program after device power -on. the fag will be low when in the sleep or idle0 mode but after power on reset or a wake-up has occurred, the fag will change to a high level after 15~16 clock cycles if the hirc oscillator is used. bit 1 idlen: idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the hal t instruction is executed. if this bit is high, when a hal t instruction is executed the device wi ll e nter t he i dle mo de. i n t he i dle1 mo de t he c pu wi ll st op r unning but t he syst em c lock wi ll c ontinue t o ke ep t he pe ripheral fun ctions op erational, i f fsyson bit is high. if fsyson bit is low, the cpu and the system clock will all stop in idle0 mode. if the bit is low the device will enter the sleep mode when a hal t instruction is executed. bit 0 hlclk: system clock selection 0: f h /2 ~ f h /64 or f l 1: f h this bit is used to select if the f h clock or the f h /2 ~ f h /64 or f l clock is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2 ~ h /64 or f l clock will be selected. when system clock switches from the f h clock to the l clock and the f h clock will be automatically switched off to conserve power .
rev. 1.00 ? 8 ? a ? 1 ?? ? 01 ? rev. 1.00 ?9 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu ctrl register bit 7 6 5 4 3 2 1 0 name fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 0 0 bit 7 fsyson: f control in idle mode 0: disable 1: enable bit 6~3 unimplemented, read as 0. bit 2 lvrf: lvr function reset fag 0: not occur 1: occurred this bit is set to 1 when a specifc low v oltage reset situation condition occurs. this bit can only be cleared to 0 by the application program. bit 1 lrf: lvrc control register software reset fag 0: not occur 1: occurred this bit is set to 1 if the l vrc register contains any non defned l vr voltage register values. this in ef fect acts like a software reset function. this bit can only be cleared to 0 by the application program. bit 0 wrf: wdt control register software reset fag 0: not occur 1: occurred this bi t i s se t t o 1 by t he w dt cont rol re gister soft ware re set a nd c leared by t he application program. note that this bit can only be cleared to 0 by the application program.                                     
   
 
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rev. 1.00 ?8 ?a? 1?? ?01? rev. 1.00 ? 9 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu operating mode switching the devi ce c an swi tch bet ween opera ting m odes dynam ically a llowing t he use r t o se lect t he best performance/power ratio for the pres ent task in hand. in this w ay microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the hal t instruction. when a hal t instructio n is executed, whether the device enters the idle mode or the sleep mode is determined by the condit ion of the idl en bit in the smod regi ster and fsyson in the ctrl register. when t he hl clk b it swi tches t o a l ow l evel, whi ch i mplies t hat c lock so urce i s swi tched fr om the high speed clock source, fh, to the clock source, fh/2~fh/64 or fl. if the clock is from the fl, the high speed clock source will stop running to conserve power . when this happens it must be noted that the fh/16 and fh/64 internal clock sources will also stop running, which may af fect the operation o f ot her i nternal fu nctions suc h a s t he t ms. t he a ccompanying fl owchart sho ws wha t happens when the device moves between the various operating modes. normal mode to slow mode switching when r unning i n t he nor mal mo de, wh ich u ses t he h igh sp eed sy stem o scillator, a nd t herefore consumes m ore powe r, t he syst em c lock c an swi tch t o run i n t he sl ow mode by se tting t he hlclk bit to "0" and setting the cks2~cks0 bits to "000" or "001" in the smod register .this will then use the low speed system oscillator which will consume less power . users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the slow mode is sourced from the lirc oscillator and therefore requires this oscillator to be stable before full mode switching occurs. this is monitored using the lto bit in the smod register. slow mode to normal mode switching in slow mode the system uses lirc low speed system oscillator . t o switch back to the normal mode, where the high speed system oscillator is used, the hlclk bit should be set to "1" or hlclk bit is "0", but cks2~cks0 is set to "010", "011", "100", "101", "110" or "111". as a certain amount of time will be required for the high frequency clock to stabili se, the status of the ht o bit is checked. the amount of time required for high speed system oscillat or stabilization depends upon which high speed system oscillator type is used.
rev. 1.00 40 ? a ? 1 ?? ? 01 ? rev. 1.00 41 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu                       
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rev. 1.00 40 ?a? 1?? ?01? rev. 1.00 41 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu entering the sleep mode there is only one way for the device to enter the sleep mode and that is to execute the "hal t" instruction in the application program with the idlen bit in smod register equal to "0". when this instruction is executed under the conditions described above, the following will occur: ? the system clock and t ime base clock will be stopped and the application program will stop at the "hal t" instruction. but the wdt or l vd will remain with the clock source coming from the f l clock. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting. ? the i/o ports will maintain their present conditions. ? in the status register , the power down fag, pdf , will be set and the w atchdog time-out fag, t o, will be cleared. entering the idle0 mode there is only one way for the device to enter the idle0 mode and that is to execute the "hal t" instruction in the application program with the idlen bit in smod register equal to "1" and the fsyson bit in ctrl register equal to "0". when this instruction is executed under the conditions described above, the following will occur: ? the syst em c lock wi ll be st opped a nd t he a pplication progra m wi ll st op a t t he "hal t" instruction, but the t ime base clock f tbc and the low frequency f l clock will be on. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting. ? the i/o ports will maintain their present conditions. ? in the status register , the power down fag, pdf , will be set and the w atchdog time-out fag, t o, will be cleared. entering the idle1 mode there is only one way for the device to enter the idle1 mode and that is to execute the "hal t" instruction in the application program with the idlen bit in smod register equal to "1" and the fsyson bit in ctrl register equal to "1". when this instruction is executed under the conditions described above, the following will occur: ? the system clock and t ime base clock and f tbc and the low frequency f l will be on and the application program will stop at the "halt" instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting. ? the i/o ports will maintain their present conditions. ? in the status register , the power down fag, pdf , will be set and the w atchdog time-out fag, t o, will be cleared.
rev. 1.00 4 ? ? a ? 1 ?? ? 01 ? rev. 1.00 4? ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode , t here a re ot her c onsiderations whi ch m ust a lso be t aken i nto a ccount by t he c ircuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fxed high or low level as any foating input pins could create internal oscillations and result in increased current consumption. this also applies to devices which have dif ferent package types, as there may be unbonbed pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. t hese shoul d be pl aced i n a c ondition i n whi ch m inimum c urrent i s dra wn or c onnected only to external circuits that do not draw current, such as other cmos inputs. in the idle1 mode the system oscillator is on, if the system oscillator is from the high speed system oscillator , the additional standby current will also be perhaps in the order of several hundred micro-amps. wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external falling edge on port a ? a system interrupt ? a wdt overfow if the device is woken up by a wdt overfow , a w atchdog t imer reset will be initiated. the actual source of the wake-up can be determined by examining the t o and pdf flags. the pdf flag is cleared by a sys tem power -up or executing the clear w atchdog t imer instructions and is set w hen executing the "hal t" instruction. the t o fag is set if a wdt time-out occurs, and causes a wake- up that only resets the program counter and stack pointer , the other fags remain in their original status. each pin on port a can be setup using the p awu register to permit a negative transition on the pin to wake-up t he syste m. when a port a pin wake-up occurs, the progra m wil l resume exec ution at the instruction following the "hal t" instruction. if the system is woken up by an interrupt, then two possible situations may occur . the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "hal t" instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag i s se t hi gh be fore e ntering t he sle ep or idl e mode, t he wa ke-up func tion of t he re lated interrupt will be disabled.
rev. 1.00 4? ?a? 1?? ?01? rev. 1.00 4 ? ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu watchdog timer the w atchdog t imer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the w atchdog t imer clock source is provided by the internal f s clock which is in turn supplied by the lirc oscillator . the w atchdog t imer source clock is then subdivided by a ratio of 2 8 t o 2 18 t o gi ve l onger t imeouts, t he a ctual va lue be ing c hosen usi ng t he w s2~ws0 bi ts i n t he w dtc register. the lirc internal oscillato r has an approximate period of 32khz at a supply voltage of 5v . however, it should be noted that this specifed internal clock period can vary with v dd , temperature and process variations. note that the w atchdog t imer function is always enabled, it can be controlled by wdtc register. watchdog timer control register a single register , wdtc, controls the required timeout period as well as the enable operation. the wdtc regis ter is initiated to 0101001 1b at any res et but keeps unchanged at the wd t time-out occurrence in a power down state. wdtc register bit 7 6 5 4 3 2 1 0 name we4 we ? we ? we1 we0 ws ? ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7~ 3 : wdt function sorgware control 10101 or 01010: enabled other values: reset mcu (reset will be active after 1~2 lirc clock for debounce time.) when these bits are changed by the environmental noise to reset the microcontroller , the wrf bit in the ctrl register will be set to 1. bit 2~ 0 : wdt t ime-out period selection 000: 2 8 /f s 001: 2 10 /f s 010: 2 12 /f s 011: 2 14 /f s 100: 2 15 /f s 101: 2 16 /f s 110: 2 17 /f s 111: 2 18 /f s these three bits determine the divis ion ratio of the w atchdog t imer s ource clock, which in turn determines the timeout period.
rev. 1.00 44 ? a ? 1 ?? ? 01 ? rev. 1.00 45 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu ctrl register bit 7 6 5 4 3 2 1 0 name fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 0 0 bit 7 fsyson: f control idle mode describe elsewhere bit 6~ 3 unimplemented, read as "0" bit 2 lvrf: lvr function reset fag describe elsewhere bit 1 lrf: lvr control register software reset fag describe elsewhere bit 0 wrf: wdt control register software reset fag 0: not occur 1: occurred this bit is set to 1 by the wdt control register software reset and cleared by the application pr ogram. not e t hat t his bi t c an on ly be c leared t o 0 by t he a pplication program. watchdog timer operation the w atchdog t imer ope rates by provi ding a de vice re set whe n i ts t imer ove rfows. t his m eans that i n t he a pplication pro gram a nd dur ing nor mal ope ration t he use r ha s t o st rategically c lear t he watchdog t imer before it overfows to prevent the w atchdog t imer from executing a reset. this is done using the cle ar watchdog instructions. if the program malfunction s for whatever reason, jumps to an unknown location, or enters an endless loop, the clear wdt instruction will not be executed in the correct manne r, in which case the w atchdog t imer will overfow and reset the device. there are fve bits, we4~we0, in the wdtc register to enable the wdt function. when the we4~we0 bits value is equal to 01010b or 10101b, the wdt function is enabled. however , if the we4~we0 bits are changed to any other values except 01010b and 10101b, which is caused by the environmental noise, it will reset the microcontroller after 2~3 lirc clock cycles. we4 ~ we0 bits wdt function 01010b or 10101b enable an ? other values reset ? cu watchdog timer enable/disable control under norm al progra m ope ration, a w atchdog t imer t ime-out wi ll i nitialise a de vice re set a nd se t the status bit t o. however , if the system is in the sleep or idle mode, when a w atchdog t imer time-out occurs, the t o bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the w atchdog t imer. the frst is a wdt reset, which means a certain value is written into the we4~we0 bit fled except 01010b and 10101b, the second is using the w atchdog t imer software clear instruction and the third is via a halt instruction. there is only one method of using software instruction to clear the w atchdog t imer. that is to use the single "clr wdt" instruction to clear the wdt .
rev. 1.00 44 ?a? 1?? ?01? rev. 1.00 45 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu the maximum time-out period is when the 2 18 division ratio is selected. as an example, with a 32 khz lirc oscillator as its source clock, this will give a maximum watchdog period of around 8 seconds for the 2 18 division ratio, and a minimum timeout of 7.8ms for the 2 8 division ration.              
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 ?   watchdog timer reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller . in this case, internal circuitry will ensure that the mi crocontroller, after a short del ay, will be in a well defined state and rea dy to execute t he fr st p rogram i nstruction. af ter t his p ower-on r eset, c ertain i mportant i nternal r egisters will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. another type of reset is w hen the w atchdog t imer overflow s and resets the microcontroller . a ll types of reset operations result in different register conditions being setup. another reset exists in the form of a low v oltage reset, l vr, where a full reset is implemented in situations where the power supply voltage falls below a certain threshold. reset functions there are four ways in which a microcontroller reset can occur, through events occurring internally: power-on reset the m ost fund amental a nd una voidable re set i s t he one t hat oc curs a fter powe r i s frst a pplied t o the microcontroller . as well as ensuring that the program memory begins execution from the frst memory address, a pow er-on reset als o ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs.                 note: t rstd is power-on delay, typical time=50ms power-on reset timing chart
rev. 1.00 46 ? a ? 1 ?? ? 01 ? rev. 1.00 47 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu low voltage reset C lvr the micr ocontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. the l vr function is always enabled with a specifc l vr voltag e, v lvr . if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery , the l vr will automatically reset the device internally and the l vrf bit in the ctrl register will also be s et to1. f or a valid l vr s ignal, a low voltage, i.e., a voltage in the range betw een 0.9v ~ v lvr must exist for greater than the value t lvr specifed in the a.c. characteristics. if the low voltage state does not exceed this value, the l vr will ignore the low supply voltage and will not perform a reset function. the actual v lvr is fxed at a voltage value of 3.15v by the l vs bits in the l vrc register. if the l vs7~lvs0 bits are changed to some certain values by the environmental noise, the lvr will reset the device after 2~3 lirc clock cycles. when this happens, the lrf bit in the ctrl register will be set to 1. after power on the register will have the value of 01010101b.                 note:t rstd is power-on delay, typical time=16.7ms low voltage reset timing chart ? lvrc register bit 7 6 5 4 3 2 1 0 name lvs7 lvs6 lvs5 lvs4 lvs ? lvs ? lvs1 lvs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 1 0 1 bit 7 ~ 0 l vs7 ~ lvs0 : lvr v oltage select control 01010101: 3.15v 00110011: 3.15v 10011001:3.15v 10101010:3.15v other values: mcu reset C (reset will be active after 2~3 lirc clock for debounce time) note: s/w can write 00h~ffh to control l vr voltage, even to s/w reset mcu. if the mcu reset caused lvrc software reset, the lrf fag of ctrl register will be set. ? ctrl register bit 7 6 5 4 3 2 1 0 name fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 0 0 bit 7 fsyson: f control idle mode describe elsewhere bit 6~ 3 unimplemented, read as "0" bit 2 lvrf: lvr function reset fag 0: not occur 1: occurred this bit is set to 1 when a specifc low v oltage reset situation condition occurs. this bit can only be cleared to 0 by the application program. bit 1 lrf: lvr control register software reset fag 0: not occur 1: occurred this bit is set to 1 if the l vrc register contains any non defned l vr voltage register values. this in ef fect acts like a software reset function. this bit can only be cleared to 0 by the application program. bit 0 wrf: wdt control register software reset fag describe elsewhere
rev. 1.00 46 ?a? 1?? ?01? rev. 1.00 47 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu watchdog time-out reset during normal operation the w atchdog time-out flag t o will be set to "1" when w atchdog time-out reset during normal operation.                    note: t rstd is power-on delay, typical time=16.7ms wdt time-out reset during normal operation timing chart watchdog time-out reset during sleep or idle mode the w atchdog time-out reset during sleep or idle mode is a little dif ferent from other kinds of re set. mo st of t he c onditions re main unc hanged e xcept t hat t he pro gram count er a nd t he st ack pointer will be cleared to "0" and the t o fag will be set to "1". refer to the a.c. characteristics for t sst details.               note: the t sst is 15~16 clock cycles if the system clock source is provided by the hirc. the t sst is 1~2 clock for the lirc. wdt time-out reset during sleep or idle timing chart reset initial conditions the dif ferent types of reset described af fect the reset fags in dif ferent ways. these fags, known as p df and t o are located in the s tatus regis ter and are controlled by various microcontroller operations, su ch a s t he sl eep o r i dle mo de f unction o r w atchdog t imer. t he r eset f lags a re shown in the table: to pdf reset conditions 0 0 power-on reset u u lvr reset during nor ? al or slow ? ode operation 1 u wdt time-out reset during nor ? al or slow ? ode operation 1 1 wdt time-out reset during idle or sleep ? ode operation note: "u" stands for unchanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset program counter reset to zero interrupts all interrupts will be disabled wdt clear after reset ? wdt begins counting timer ? odules timer ? odules will be turned off input/output ports i/o ports will be setup as inputs and an0~an5 as a/d input pins stack pointer stack pointer will point to the top of the stack
rev. 1.00 48 ? a ? 1 ?? ? 01 ? rev. 1.00 49 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu the dif ferent kinds of resets all af fect the internal registers of the micr ocontroller in dif ferent ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. register reset (power on) wdt time-out (normal operation) lvr reset wdt time-out (sleep/idle) ? p0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ? p1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu bp ---- ---0 ---- ---0 ---- ---0 ---- ---u acc xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu tblh xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu tbhp ---- -xxx ---- -uuu ---- -xxx ---- -uuu status --00 xxxx --1u uuuu --uu xxxx --11 uuuu s ? od 0000 0011 0000 0011 0000 0011 uuuu uuuu lvdc --00 -000 --00 -000 --00 -000 --uu Cuuu lvrc 0101 0101 0101 010 0101 0101 uuuu uuuu wdtc 0101 0011 0101 0011 0101 0011 uuuu uuuu tbc 0011 ---- 0011 ---- 0011 ---- uuuu ---- intc0 -000 0000 -000 0000 -000 0000 -uuu uuuu intc1 0000 0000 0000 0000 0000 0000 uuuu uuuu intc ? -000 -000 -000 -000 -000 -000 -uuu -uuu ? fi0 0000 0000 0000 0000 0000 0000 uuuu uuuu ? fi1 0000 0000 0000 0000 0000 0000 uuuu uuuu ? fi ? 0000 0000 0000 0000 0000 0000 uuuu uuuu ? fi ? 0000 0000 0000 0000 0000 0000 uuuu uuuu ? fi4 --00 --00 --00 --00 --00 --00 --uu --uu pawu 0000 0000 0000 0000 0000 0000 uuuu uuuu papu 0000 0000 0000 0000 0000 0000 uuuu uuuu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu pbpu ---- 0000 ---- 0000 ---- 0000 ---- uuuu pb ---- 1111 ---- 1111 ---- 1111 ---- uuuu pbc ---- 1111 ---- 1111 ---- 1111 ---- uuuu pcpu --00 0000 --00 0000 --00 0000 --uu uuuu pc --11 1111 --11 1111 --11 1111 --uu uuuu pcc --11 1111 --11 1111 --11 1111 --uu uuuu integ -000 0000 -000 0000 -000 0000 -uuu uuuu iicc0 ---- 000- ---- 000- ---- 000- ---- uuu- iicc1 1000 0001 1000 0001 1000 0001 uuuu uuuu iicd xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu iica xxxx xxx- xxxx xxx- xxxx xxx- uuuu uuu- i ? ctoc 0000 0000 0000 0000 0000 0000 uuuu uuuu nf_vih 00-11001 00-11001 00-11001 u--u uuuu nf_vil 00-0 1010 00-0 1010 00-0 1010 00-u uuuu hchk_nu ? ---0 0000 ---0 0000 ---0 0000 ---u uuuu hnf_ ? sel ---- 0000 ---- 0000 ---- 0000 ---- uuuu captc0 0000 0000 0000 0000 0000 0000 uuuu uuuu
rev. 1.00 48 ?a? 1?? ?01? rev. 1.00 49 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu register reset (power on) wdt time-out (normal operation) lvr reset wdt time-out (sleep/idle) captc1 0000 0000 0000 0000 0000 0000 uuuu uuuu capt ? dl 0000 0000 0000 0000 0000 0000 uuuu uuuu capt ? dh 0000 0000 0000 0000 0000 0000 uuuu uuuu capt ? al 0000 0000 0000 0000 0000 0000 uuuu uuuu capt ? ah 0000 0000 0000 0000 0000 0000 uuuu uuuu capt ? cl xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu capt ? ch xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu opo ? s 00-- -010 00-- -010 00-- -010 uu-- -uuu opc ? 0000 0000 0000 0000 0000 0000 uuuu uuuu cpc 1111 0000 1111 0000 1111 0000 uuuu uuuu ctrl 0--- -x00 0--- -x00 0--- -x00 u--- -uuu eec ---- 0000 ---- 0000 ---- 0000 ---- uuuu eea ---x xxxx ---x xxxx ---x xxxx ---u uuuu eed xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrl xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrh ---- --xx ---- --xx ---- --xx ---- --uu adcr0 011- 0000 011- 0000 011- 0000 uuu- uuuu adcr1 0000 0000 0000 0000 0000 0000 uuuu uuuu adcr ? ---- --00 ---- --00 ---- --00 ---- --uu addl 0000 0000 0000 0000 0000 0000 uuuu uuuu adlvdl 0000 0000 0000 0000 0000 0000 uuuu uuuu adlvdh xxxx xx00 xxxx xx00 xxxx xx00 uuuu uuuu adhvdl 0000 0000 0000 0000 0000 0000 uuuu uuuu adhvdh ---- --00 ---- --00 ---- --00 ---- --uu pw ? c 0000 0000 0000 0000 0000 0000 uuuu uuuu dutr0l 0000 0000 0000 0000 0000 0000 uuuu uuuu dutr0h ---- --00 ---- --00 ---- --00 ---- --uu dutr1l 0000 0000 0000 0000 0000 0000 uuuu uuuu dutr1h ---- --00 ---- --00 ---- --00 ---- --uu dutr ? l 0000 0000 0000 0000 0000 0000 uuuu uuuu dutr ? h ---- --00 ---- --00 ---- --00 ---- --uu prdrl 0000 0000 0000 0000 0000 0000 uuuu uuuu prdrh ---- --00 ---- --00 ---- --00 ---- --uu pw ? rl 0000 0000 0000 0000 0000 0000 uuuu uuuu pw ? rh ---- --00 ---- --00 ---- --00 ---- --uu ? cf 0 --- 0100 0 --- 0100 0 --- 0100 0 --- uuuu ? cd --00 0111 --00 0111 --00 0111 --uu uuuu dts 0000 0000 0000 0000 0000 0000 uuuu uuuu plc --00 0000 --00 0000 --00 0000 --uu uuuu hdcr 0001 0000 0001 0000 0001 0000 uuuu uuuu hdcd ---- -000 ---- -000 ---- -000 ---- -uuu hdct0 --00 0000 --00 0000 --00 0000 --uu uuuu hdct1 --00 0000 --00 0000 --00 0000 --uu uuuu hdct ? --00 0000 --00 0000 --00 0000 --uu uuuu hdct ? --00 0000 --00 0000 --00 0000 --uu uuuu hdct4 --00 0000 --00 0000 --00 0000 --uu uuuu hdct5 --00 0000 --00 0000 --00 0000 --uu uuuu
rev. 1.00 50 ? a ? 1 ?? ? 01 ? rev. 1.00 51 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu register reset (power on) wdt time-out (normal operation) lvr reset wdt time-out (sleep/idle) hdct6 --00 0000 --00 0000 --00 0000 --uu uuuu hdct7 --00 0000 --00 0000 --00 0000 --uu uuuu hdct8 --00 0000 --00 0000 --00 0000 --uu uuuu hdct9 --00 0000 --00 0000 --00 0000 --uu uuuu hdct10 --00 0000 --00 0000 --00 0000 --uu uuuu hdct11 --00 0000 --00 0000 --00 0000 --uu uuuu ? ptc1 0000 00-- 0000 00-- 0000 00-- uuuu uu-- ? ptc ? ---1 0011 ---1 0011 ---1 0011 ---u uuuu t ? 1c0 0000 0--- 0000 0--- 0000 0--- uuuu u--- t ? 1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu t ? 1dl 0000 0000 0000 0000 0000 0000 uuuu uuuu t ? 1dh 0000 0000 0000 0000 0000 0000 uuuu uuuu t ? 1al 0000 0000 0000 0000 0000 0000 uuuu uuuu t ? 1ah 0000 0000 0000 0000 0000 0000 uuuu uuuu t ? 1rp 0000 0000 0000 0000 0000 0000 uuuu uuuu opacal -001 0000 -001 0000 -001 0000 -uuu uuuu pw ?? e --00 0000 --00 0000 --00 0000 --uu uuuu pw ?? d --00 0000 --00 0000 --00 0000 --uu uuuu t ? 0c0 0000 0000 0000 0000 0000 0000 uuuu uuuu t ? 0c1 0000 0000 0000 0000 0000 0000 uuuu uuuu t ? 0dl 0000 0000 0000 0000 0000 0000 uuuu uuuu t ? 0dh ---- --00 ---- --00 ---- --00 ---- --uu t ? 0al 0000 0000 0000 0000 0000 0000 uuuu uuuu t ? 0ah ---- --00 ---- --00 ---- --00 ---- --uu t ?? c0 0000 0000 0000 0000 0000 0000 uuuu uuuu t ?? c1 0000 0000 0000 0000 0000 0000 uuuu uuuu t ?? dl 0000 0000 0000 0000 0000 0000 uuuu uuuu t ?? dh ---- --00 ---- --00 ---- --00 ---- --uu t ?? al 0000 0000 0000 0000 0000 0000 uuuu uuuu t ?? ah ---- --00 ---- --00 ---- --00 ---- --uu paps0 0000 0000 0000 0000 0000 0000 uuuu uuuu paps1 0000 0000 0000 0000 0000 0000 uuuu uuuu pbps0 0000 0000 0000 0000 0000 0000 uuuu uuuu pcps0 0000 0000 0000 0000 0000 0000 uuuu uuuu pcps1 ---- 0000 ---- 0000 ---- 0000 ---- uuuu pr ? ---- 0000 ---- 0000 ---- 0000 ---- uuuu note: "-" not implement "u" stands for "unchanged" "x" stands for "unknown"
rev. 1.00 50 ?a? 1?? ?01? rev. 1.00 51 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu input/output ports holtek microcontrollers of fer considerable fexibility on their i/o ports. w ith the input or output designation of e very pi n ful ly unde r use r progra m c ontrol, pul l-high se lections for a ll port s a nd wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the device provides bidirectional input/output lines labeled with port names p a, pb and pc. these i/o ports are mapped to the ram data memory with specifc addresses as shown in the special purpose data memory table. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction "mov a, [m]", where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. i/o register list register name bit 7 6 5 4 3 2 1 0 pa d7 d6 d5 d4 d ? d ? d1 d0 pac d7 d6 d5 d4 d ? d ? d1 d0 papu d7 d6 d5 d4 d ? d ? d1 d0 pawu d7 d6 d5 d4 d ? d ? d1 d0 pb d ? d ? d1 d0 pbc d ? d ? d1 d0 pbpu d ? d ? d1 d0 pc d5 d4 d ? d ? d1 d0 pcc d5 d4 d ? d ? d1 d0 pcpu d5 d4 d ? d ? d1 d0 pull-high resistors many produc t applic ations requi re pull-high resist ors for thei r swit ch inputs usuall y requi ring the use of an external resistor . t o eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capa bility of being connected to an inte rnal pull-high resistor . these pull-high resi stors a re se lected usi ng regi sters p apu~pcpu, a nd a re i mplemented usi ng we ak pmos transistors. papu register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 0 i/o port a bit7~ bit 0 pull-high control 0: disable 1: enable
rev. 1.00 5 ? ? a ? 1 ?? ? 01 ? rev. 1.00 5? ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu pbpu register bit 7 6 5 4 3 2 1 0 name d ? d ? d1 d0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 ~ 4 unimplemented, read as "0" bit 3 ~ 0 i/o port b bit3~ bit 0 pull-high control 0: disable 1: enable pcpu register bit 7 6 5 4 3 2 1 0 name d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 ~ 6 unimplemented, read as "0" bit 5 ~ 0 i/o port c bit5~ bit 0 pull-high control 0: disable 1: enable port a wake-up the hal t instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. v arious methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low . this function is especially suitable for applications that can be woken up via extern al switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. pawu register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 0 i/o port a bit 7 ~ bit 0 w ake up control 0: disable 1: enable
rev. 1.00 5? ?a? 1?? ?01? rev. 1.00 5 ? ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu i/o port control registers each i/o port has its own control register known as p ac~pcc, to control the input/output configuration. w ith this control register , each cmos output or input can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register . for the i/o pin to function as an input, the corresponding bit of the control register must be written as a "1". this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a "0", the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register . however , it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pac register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7 ~ 0 i/o port a bit 7~bit 0 input/output control 0: output 1: input pbc register bit 7 6 5 4 3 2 1 0 name d ? d ? d1 d0 r/w r/w r/w r/w r/w por 1 1 1 1 bit 7 ~ 4 unimplemented, read as "0" bit 3 ~ 0 i/o port b bit3~bit 0 input/output control 0: output 1: input pcc register bit 7 6 5 4 3 2 1 0 name d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 bit 7 ~ 6 unimplemented, read as "0" bit 5 ~ 0 i/o port c bit 5~bit 0 input/output control 0: output 1: input
rev. 1.00 54 ? a ? 1 ?? ? 01 ? rev. 1.00 55 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu pin-sharing functions paps0 register bit 7 6 5 4 3 2 1 0 name pa ? s1 pa ? s0 pa ? s1 pa ? s0 pa1s1 pa1s0 pa0s1 pa0s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 6 pa3s1~pa3s0: pa3 pin share setting 00: pa3/tck2/h1 01: c1p 10: pa3/tck2/h1 11: pa3/tck2/h1 bit 5 ~ 4 pa2s1~pa2s0: pa2 pin share setting 00: pa2 01: scl 10: pa2 11: pa2 bit 3 ~ 2 pa1s1~pa1s0: pa1 pin share setting 00: pa1/tck3 01: an2/ap 10: pa1/tck3 11: pa1/tck3 bit 1 ~ 0 pa0s1~pa0s0: pa0 pin share setting 00: pa0 01: sda 10: pa0 11: pa0 paps1 register bit 7 6 5 4 3 2 1 0 name pa7s1 pa7s0 pa6s1 pa6s0 pa5s1 pa5s0 pa4s1 pa4s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 6 pa7s1~pa7s0: pa7 pin share setting 00: pa7/nfin 01: an1 10: pa7/nfin 11: pa7/nfin bit 5 ~ 4 pa6s1~pa6s0: pa6 pin share setting 00: pa6 01: [c1n] if pin-remap enabled 10: an0 11: pa6 bit 3 ~ 2 pa5s1~pa5s0: pa5 pin share setting 00: pa5/h3 01: [scl] if pin-remap enabled 10: c3p 11: pa5/h3 bit 1 ~ 0 pa4s1~pa4s0: pa4 pin share setting 00: pa4/h2 01: [sda] if pin-remap enabled 10: c2p 11: [c1n] if pin-remap enabled
rev. 1.00 54 ?a? 1?? ?01? rev. 1.00 55 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu pbps0 register bit 7 6 5 4 3 2 1 0 name pb ? s1 pb ? s0 pb ? s1 pb ? s0 pb1s1 pb1s0 pb0s1 pb0s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 6 pb3s1~pb3s0: pb3 pin share setting 00: pb3/tck1 01: c1n if pin-remap disabled 10: pb3/tck1 11: pb3/tck1 bit 5 ~ 4 pb2s1~pb2s0: pb2 pin share setting 00: pb2 01: hco 10: an5 11: pb2 bit 3 ~ 2 pb1s1~pb1s0: pb1 pin share setting 00: pb1/ctin 01: hbo 10: an4 11: pb1/ctin bit 1 ~ 0 pb0s1~pb0s0: pb0 pin share setting 00: pb0 01: hao 10: an3 11: pb0 pcps0 register bit 7 6 5 4 3 2 1 0 name pc ? s1 pc ? s0 pc ? s1 pc ? s0 pc1s1 pc1s0 pc0s1 pc0s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 6 pc3s1~pc3s0: pc3 pin share setting 00: pc3 01: tp1_1 10: gbb 11: pc3 bit 5 ~ 4 pc2s1~pc2s0: pc2 pin share setting 00: pc2 01: tp1_0 10: gbt 11: pc2 bit 3 ~ 2 pc1s1~pc1s0: pc1 pin share setting 00: pc1 01: tp0_1 10: gab 11: pc1 bit 1 ~ 0 pc0s1~pc0s0: pc0 pin share setting 00: pc0 01: tp0_0 10: gat 11: pc0
rev. 1.00 56 ? a ? 1 ?? ? 01 ? rev. 1.00 57 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu pcps1 register bit 7 6 5 4 3 2 1 0 name pc5s1 pc5s0 pc4s1 pc4s0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 ~ 4 unimplemented, read as "0" bit 3 ~ 2 pc5s1~pc5s0: pc5 pin share setting 00: pc5 01: tp2_1 10: gcb 11: pc5 bit 1 ~ 0 pc4s1~p c4s0: pc4 pin share setting 00: pc4 01: tp2_0 10: gct 11: pc4 pin-remapping functions the fexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pi ns can forc e seri ous design constraints on de signers but by supplyi ng pi ns with multi-functions, many of these diffculties can be overcome. the way in which the pin function of each pin is selected is dif ferent for each function and a priority order is established where more than one pin function is selected simultaneously . additionally there are a series of prm register to establish certain pin functions. pin-remapping registers the limited number of supplied pins in a package can i mpose restrictions on the amount of functions a certain device can contain. however by allowing the same pins to share several dif ferent functions and providing a means of function selection, a wide range of dif ferent functions can be incorporated into even relatively small package sizes. some devices include prm register which can select the functions of certain pins. prm register bit 7 6 5 4 3 2 1 0 name c1nps1 c1nps0 sdaps sclps r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 ~ 4 unimplemented, read as "0" bit 3 ~ 2 c1nps1~c1nps0: 00: c1n on pb3 01: c1n on pa6 10: c1n on pa4 11: c1n reserved bit 1 sdaps: 0: sda on pa0 1: sda on pa4 bit 0 sclps: 0: scl on pa2 1: scl on pa5
rev. 1.00 56 ?a? 1?? ?01? rev. 1.00 57 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will dif fer from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown.                    
                                           
                       ???     ??     ?   ?  ?          generic input/output structure                        
                         
                         ?    ?  
 ?  ?          ?   ? -  ?  ? -  ?  ? ?        ? a/d input/output structure
rev. 1.00 58 ? a ? 1 ?? ? 01 ? rev. 1.00 59 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu programming considerations within the user program, one of the frst things to consider is port initi alisation. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an i nput st ate, t he l evel of whi ch de pends on t he ot her c onnected c ircuitry a nd whe ther pul l-high selections have been chosen. if the port control registers, p ac~pcc, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, p a~pc, are frst programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the "set [m].i" and "clr [m].i" instructions . n ote that w hen us ing thes e bit control instructions , a read-modify-w rite operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function. timer modules C tm one of the most fundamental functions in any microcontroller device is the ability to control and measure time. t o implement time related functions the device includes several t imer modules, abbreviated t o t he na me t m. t he t ms a re m ulti-purpose t iming un its a nd se rve t o pr ovide operations such as t imer/counter, input capture, compare match output and single pulse output as we ll a s be ing t he fun ctional uni t for t he ge neration of pw m si gnals. e ach of t he t ms ha s t wo individual interrupts. the addition of input and output pins for each tm ensures that users are provided with timing units with a wide and fexible range of features. the common features of the dif ferent tm types are described here with more detailed information provided in the individual compact and standard tm section. introduction the device contai ns three tms, a 10-bit compact tm, a 16-bit compact tm and a 10-bit standard tm, each tm having a reference name of tm0, tm1 and tm2. although similar in nature, the different tm types vary in their feature complexity . the common features to the compact and standard tms will be described in this section and the detailed operation will be described in corresponding sec tions. the ma in feat ures and dif ferences bet ween the two types of tms are summarised in the accompanying table. function ctm stm timer/counter i/p capture compare ? atch output pw ? channels 1 1 single pulse output pw ? alignment edge edge pw ? adjustment period & dut ? dut ? or period dut ? or period tm function summary tm0 tm1 tm2 10-bit ct ? 16-bit ct ? 10-bit st ? tm name/type reference
rev. 1.00 58 ?a? 1?? ?01? rev. 1.00 59 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu tm operation the t wo d ifferent t ypes o f t ms o ffer a d iverse r ange o f f unctions, f rom si mple t iming o perations to pwm signal generation. the key to understanding how the tm operates is to see it in terms of a fre e runni ng c ounter who se va lue i s t hen c ompared wi th t he va lue of pre -programmed i nternal comparators. when the free running counter has the same value as the pre-programmed comparator , known a s a c ompare m atch si tuation, a t m i nterrupt si gnal wi ll be ge nerated whi ch c an c lear t he counter a nd pe rhaps a lso c hange t he c ondition of t he t m ou tput pi n. t he i nternal t m c ounter i s driven by a user selectable clock source, which can be an internal clock or an external pin. tm clock source the c lock so urce wh ich d rives t he m ain c ounter i n e ach t m c an o riginate f rom v arious so urces. the selection of the required clock source is implemented using the tnck2~tnck0 bits in the tm control registers. the clock source can be a ratio of either the system clock f sys or the internal high clock f h , the f tbc clock source or the external tckn pin. the tckn pin clock source is used to allow an external signal to drive the tm as an external clock source or for event counting. tm interrupts the two different types of tms have two internal interrupts, the internal comparator a or comparator p, which generate a tm interrupt when a compare match condition occurs. when a tm interrupt is generated, it can be used to clear the counter and also to change the state of the tm output pin. tm external pins each of the tms, irrespective of what type, has one tm input pin, with the label tckn. the tm input pin, is essentially a clock source for the tm and is selected using the tnck2~tnck0 bits in the tmnc0 register . this external tm input pin allows an external clock source to drive the internal tm. this external tm input pin is shared with other functions but will be connected to the internal tm i f se lected u sing t he t nck2~tnck0 b its. t he t m i nput p in c an b e c hosen t o h ave e ither a rising or falling active edge. the t ms e ach ha ve two ou tput pi ns. w hen t he t m i s i n t he co mpare ma tch out put mod e, t hese pins can be controlled by the tm to switch to a high or low level or to toggle when a compare match situation occurs. the external tpn output pin is also the pin where the tm generates the pwm output waveform. as the tm output pins are pin-shared with other function, the tm output function must frst be setup using registers. a single bit in one of the registers determines if its associated pin is to be used as an external tm output pin or if it is to have another function. the number of output pins for each tm type is different, the details are provided in the accompanying table. all tm output pin names have an "_n" suffx. pin names that include a "_0" or "_1" suffx indicate that they are from a tm with multiple output pins. this allows the tm to generate a complimentary output pair, selected using the i/o register data bits. tm0 tm1 tm2 tp0_0 ? tp0_1 tp1_0 ? tp1_1 tp ? _0 ? tp ? _1 tm output pins
rev. 1.00 60 ? a ? 1 ?? ? 01 ? rev. 1.00 61 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu programming considerations the tm counter registers, the capture/compare ccra register , being either 16-bit or 10-bit, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buf fer, reading or writing to these register pairs must be carried out in a specifc way . the important point to note is that data transfer to and from the 8-bit buffer and its rela ted low byte only takes place when a write or read operation to its corresponding high byte is executed. as t he ccra re gister i s i mplemented i n t he wa y shown i n t he fol lowing di agram a nd a ccessing these register pairs is carried out in a specifc way described above, it is recommended to use the "mov" instruct ion to acce ss the ccra low byte re gisters, named tmxal, using the foll owing access procedures. accessing the ccra low byte register without following these access procedures will result in unpredictable values. data bus 8- bit buffer t?xdh t?xdl t?xah t?xal t? counter register ( read onl? ) t? ccra register ( read / write ) the following steps show the read and write procedures: ? writing data to ccra ? step 1. w rite data to low byte tmxal C note that here data is only written to the 8-bit buffer. ? step 2. w rite data to high byte tmxah C here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the low byte registers. ? reading data from the counter registers and ccra ? step 1. read data from the high byte tmxdh or tmxah C he re da ta i s re ad di rectly from t he hi gh byt e re gisters a nd si multaneously da ta i s l atched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte tmxdl or tmxal C this step reads data from the 8-bit buffer.
rev. 1.00 60 ?a? 1?? ?01? rev. 1.00 61 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu compact type tm C ctm although the simplest form of the tm types, the compact tm type still contains three operating modes, wh ich a re c ompare ma tch ou tput, t imer/event c ounter a nd pw m ou tput m odes. t he compact t m c an a lso be c ontrolled wi th a n e xternal i nput pi n a nd c an dri ve t wo e xternal out put pins. these two external output pins can be the same signal or the inverse signal.                         
           ?     ?         ?    ??         ??  ??   ?   ??   ?  ?   ??  ? -  ? ?   ? -  ? ?    ? 
?  ?         ?    -
?  -
 
 
  ? ? ?    ?
?  ?    ?  ?  ?           ? ??? ?? ? ??? ? ? ? ? ? ? ?? ? ? ?  ? ?? ? ??  compact type tm block diagram (n=0, 1) compact tm operation at i ts c ore i s a 10-bi t or 16-bi t c ount-up c ounter whi ch i s dri ven by a use r se lectable i nternal or external clock source. there are also two internal comparators with the names, comparator a and comparator p . these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp is three bits wide whose value is compared with the highest three bits or eight bits in the counter while the ccra is the ten bits or sixteen bits and therefore compares with all counter bits. the only way of changing the value of the 10-bit or 16-bit counter using the application program, is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur , a tm interrupt signal will also usually be generated. the compact type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers.
rev. 1.00 6 ? ? a ? 1 ?? ? 01 ? rev. 1.00 6? ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu compact type tm register description overall operation of the compact tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10-bit or 16-bit value, while a read/write register pair exists to store the intern al 10-bit or 16-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three or eight ccrp bits. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t ? 0c0 t0pau t0ck ? t0ck1 t0ck0 t0on t0rp ? t0rp1 t0rp0 t ? 0c1 t0 ? 1 t0 ? 0 t0io1 t0io0 t0oc t0pol t0dpx t0cclr t ? 0dl d7 d6 d5 d4 d ? d ? d1 d0 t ? 0dh d9 d8 t ? 0al d7 d6 d5 d4 d ? d ? d1 d0 t ? 0ah d9 d8 10-bit compact tm register list name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t ? 1c0 t1pau t1ck ? t1ck1 t1ck0 t1on t ? 1c1 t1 ? 1 t1 ? 0 t1io1 t1io0 t1oc t1pol t1dpx t1cclr t ? 1dl d7 d6 d5 d4 d ? d ? d1 d0 t ? 1dh d15 d14 d1 ? d1 ? d11 d10 d9 d8 t ? 1al d7 d6 d5 d4 d ? d ? d1 d0 t ? 1ah d15 d14 d1 ? d1 ? d11 d10 d9 d8 t ? 1rp d7 d6 d5 d4 d ? d ? d1 d0 16-bit compact tm register list tm0dl register C 10-bit ctm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm0dl: tm0 counter low byte register bit 7~bit 0 tm0 10-bit counter bit 7~bit 0 tm0dh register C 10-bit ctm bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tm0dh: tm0 counter high byte register bit 1~bit 0 tm0 10-bit counter bit 9~bit 8 tm0al register(n=0) C 10-bit ctm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm0al: tm0 ccra low byte register bit 7~bit 0 tm0 10-bit ccra bit 7~bit 0
rev. 1.00 6? ?a? 1?? ?01? rev. 1.00 6 ? ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu tm0ah register C 10-bit ctm bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tm0ah: tm0 ccra high byte register bit 1~bit 0 tm0 10-bit ccra bit 9~bit 8 tm1dl register C 16-bit ctm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm1dl: tm1 counter low byte register bit 7~bit 0 tm1 16-bit counter bit 7~bit 0 tm1dh register C 16-bit ctm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm1dh: tm1 counter high byte register bit 7~bit 0 tm1 16-bit counter bit 15~bit 8 tm1al register C 16-bit ctm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm1al: tm1 ccra low byte register bit 7~bit 0 tm1 16-bit ccra bit 7~bit 0 tm1ah register C 16-bit ctm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm1ah: tm1 ccra high byte register bit 7~bit 0 tm1 16-bit ccra bit 15~bit 8
rev. 1.00 64 ? a ? 1 ?? ? 01 ? rev. 1.00 65 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu tm0c0 register C 10-bit ctm bit 7 6 5 4 3 2 1 0 name t0pau t0ck ? t0ck1 t0ck0 t0on t0rp ? t0rp1 t0rp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t0pau: tm0 counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t0ck2~t0ck0: select tm0 counter clock 000: f /4 001: f 010: f h /16 011: f h /64 100: f tbc 101: reserved 110: tck0 rising edge clock 111: tck0 falling edge clock these three bits are used to select the clock source for the tm0. selecting the reserved clock input will ef fectively disable the internal counter . the external pin clock source can be chosen to be active on the rising or falling edge. the clock source is the system clock, while f h and f tbc are other internal clocks, the details of which can be found in the oscillator section. bit 3 t0on: tm0 counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tm0. setting the bit high enables the counter to run, clearing the bit disables the tm0. clearing this bit to zero will stop the counter from counting and turn of f the tm0 which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value. if the tm0 is in the compare match output mode then the tm0 output pin will be reset to its initial condition, as specifed by the t0oc bit, when the t0on bit changes from low to high. bit 2~0 t0rp2~t0rp0: tm0 ccrp 3-bit register, compared with the tm0 counter bit 9~bit 7 comparator p match period 000: 1024 tm0 clocks 001: 128 tm0 clocks 010: 256 tm0 clocks 011: 384 tm0 clocks 100: 512 tm0 clocks 101: 640 tm0 clocks 110: 768 tm0 clocks 111: 896 tm0 clocks these three bits are used to setup the value on the internal ccrp 3-bit register , which are then compared with the internal counter s highest three bits. the result of this comparison c an be se lected t o c lear t he i nternal c ounter i f t he t 0cclr bi t i s se t t o zero. set ting t he t 0cclr bi t t o z ero e nsures t hat a c ompare m atch wi th t he ccrp values will reset the internal counter . as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing a ll t hree bi ts t o z ero i s i n e ffect a llowing t he c ounter t o ove rflow a t i ts maximum value .
rev. 1.00 64 ?a? 1?? ?01? rev. 1.00 65 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu tm0c1 register C 10-bit ctm bit 7 6 5 4 3 2 1 0 name t0 ? 1 t0 ? 0 t0io1 t0io0 t0oc t0pol t0dpx t0cclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 t0m1~t0m0: select tm0 operating mode 00: compare match output mode 01: undefned 10: pwm mode 11: t imer/counter mode these bits setup the required operating mode for the tm. t o ensure reliable operation the tm should be switched of f before any changes are made to the t0m1 and t0m0 bits. in the t imer/counter mode, the tm output pin control must be disabled. bit 5~4 t0io1~t0io0: select tp0_0, tp0_1 output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: undefned timer/counter mode unused these two bits are used to determine how the tm0 output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm0 is running. in t he com pare ma tch out put mode , t he t 0io1 a nd t 0io0 bi ts de termine how t he tm0 output pin changes state when a compare match occurs from the comparator a. the t m0 ou tput pi n c an be se tup t o swi tch hi gh, swi tch l ow or t o t oggle i ts pr esent state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm0 output pin should be setup using the t0oc bit in the tm0c1 register . note that the output level requested by the t0io1 and t0io0 bits must be dif ferent from the initial value setup using the t0oc bit otherwise no change will occur on the tm0 output pin when a compare match occurs. after the tm0 output pin changes state it can be reset to its initial level by changing the level of the t0on bit from low to high. in the pwm mode, the t0io1 and t0io0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function i s m odified b y c hanging t hese t wo b its. i t i s n ecessary t o o nly c hange t he values of t he t 0io1 a nd t 0io0 bi ts onl y a fter t he t m0 ha s be en swi tched of f. unpredictable pwm outputs will occur if the t 0io1 and t 0io0 bits are changed when the tm is running.
rev. 1.00 66 ? a ? 1 ?? ? 01 ? rev. 1.00 67 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu bit 3 t0oc: tp0_0, tp0_1 output control bit compare match output mode 0: initial low 1: initial high pwm mode 0: active low 1: active high this is the output control bit for the tm0 output pin. its operation depends upon whether tm0 is being used in the compare match output mode or in the pwm mode. it has no ef fect if the tm0 is in the t imer/counter mode. in the compare match output mode i t de termines t he l ogic l evel of he t m0 ou tput pi n be fore a c ompare match oc curs. in t he pwm mode i t det ermines i f t he pwm si gnal i s a ctive hi gh or active low. bit 2 t0pol: tp0_0, tp0_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp0_0 or tp0_1 output pin. when the bit is set high the tm0 output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm0 is in the t imer/counter mode. bit 1 t0dpx: tm0 pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 t0cclr: select tm0 counter clear condition 0: tm0 comparator p match 1: tm0 comparator a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he compact t m0 c ontains t wo c omparators, c omparator a a nd c omparator p , e ither of which can be selected to clear the internal counter . w ith the t0cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the t0cclr bit is not used in the pwm mode.
rev. 1.00 66 ?a? 1?? ?01? rev. 1.00 67 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu tm1c0 register C 16-bit ctm bit 7 6 5 4 3 2 1 0 name t1pau t1ck ? t1ck1 t1ck0 t1on r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 t1pau: tm1 counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t1ck2~t1ck0: select tm1 counter clock 000: f /4 001: f 010: f h /16 011: f h /64 100: f tbc 101: reserved 110: tck1 rising edge clock 111: tck1 falling edge clock these three bits are used to select the clock source for the tm1. selecting the reserved clock input will ef fectively disable the internal counter . the external pin clock source can be chosen to be active on the rising or falling edge. the clock source is the system clock, while f h and f tbc are other internal clocks, the details of which can be found in the oscillator section . bit 3 t1on: tm1 counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tm1. setting the bit high enables the counter to run, clearing the bit disables the tm1. clearing this bit to zero will stop the counter from counting and turn of f the tm1 which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value. if the tm1 is in the compare match output mode then the tm1 output pin will be reset to its initial condition, as specifed by the t1oc bit, when the t1on bit changes from low to high. bit 2~0 unimplemented, read as "0"
rev. 1.00 68 ? a ? 1 ?? ? 01 ? rev. 1.00 69 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu tm1c1 register C 16-bit ctm bit 7 6 5 4 3 2 1 0 name t1 ? 1 t1 ? 0 t1io1 t1io0 t1oc t1pol t1dpx t1cclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 t1m1~t1m0: select tm1 operating mode 00: compare match output mode 01: undefned 10: pwm mode 11: t imer/counter mode these bits setup the required operating mode for the tm. t o ensure reliable operation the tm should be switched of f before any changes are made to the t1m1 and t1m0 bits. in the t imer/counter mode, the tm output pin control must be disabled. bit 5~4 t1io1~t1io0: select tp1_0, tp1_1 output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: undefned timer/counter mode unused these two bits are used to determine how the tm1 output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm1 is running. in t he com pare ma tch out put mode , t he t 1io1 a nd t 1io0 bi ts de termine how t he tm1 output pin changes state when a compare match occurs from the comparator a. the t m1 ou tput pi n c an be se tup t o swi tch hi gh, swi tch l ow or t o t oggle i ts pr esent state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm1 output pin should be setup using the t1oc bit in the tm1c1 register . note that the output level requested by the t1io1 and t1io0 bits must be dif ferent from the initial value setup using the t1oc bit otherwise no change will occur on the tm1 output pin when a compare match occurs. after the tm1 output pin changes state it can be reset to its initial level by changing the level of the t1on bit from low to high. in the pwm mode, the t1io1 and t1io0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function i s m odified b y c hanging t hese t wo b its. i t i s n ecessary t o o nly c hange t he values of t he t 1io1 a nd t 1io0 bi ts onl y a fter t he t m1 ha s be en swi tched of f. unpredictable pwm outputs will occur if the t 1io1 and t 1io0 bits are changed when the tm is running.
rev. 1.00 68 ?a? 1?? ?01? rev. 1.00 69 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu bit 3 t1oc: tp1_0, tp1_1 output control bit compare match output mode 0: initial low 1: initial high pwm mode 0: active low 1: active high this is the output control bit for the tm1 output pin. its operation depends upon whether tm1 is being used in the compare match output mode or in the pwm mode. it has no ef fect if the tm1 is in the t imer/counter mode. in the compare match output mode i t de termines t he l ogic l evel of he t m1 ou tput pi n be fore a c ompare match oc curs. in t he pwm mode i t det ermines i f t he pwm si gnal i s a ctive hi gh or active low. bit 2 t1pol: tp1_0, tp1_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp1_0 or tp1_1 output pin. when the bit is set high the tm1 output pin will be inverted and not inverted when the bit is zero. it has no effect if the tmn is in the t imer/counter mode. bit 1 t1dpx: tm1 pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 t1cclr: select tm1 counter clear condition 0: tm1 comparator p match 1: tm1 comparator a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he compact t m1 c ontains t wo c omparators, c omparator a a nd c omparator p , e ither of which can be selected to clear the internal counter . w ith the t1cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the t1cclr bit is not used in the pwm mode. tm1rp register C 16-bit ctm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm 1rp: tm 1 ccrp register bit 7~bit 0 0: 65536 tm1 clocks 1~255: 256(1~255)tm1 clocks tm1 ccrp 8-bit register , compared with the tm1 counter bit 15~bit 8 comparator p match period these three bits are used to setup the value on the internal ccrp 8-bit register , which are then compared with the internal counter s highest eight bits. the result of this comparison c an be se lected t o c lear t he i nternal c ounter i f t he t 1cclr bi t i s se t t o zero. set ting t he t 1cclr bi t t o z ero e nsures t hat a c ompare m atch wi th t he ccrp values will reset the internal counter . as the ccrp bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. clearing a ll t hree bi ts t o z ero i s i n e ffect a llowing t he c ounter t o ove rflow a t i ts maximum value.
rev. 1.00 70 ? a ? 1 ?? ? 01 ? rev. 1.00 71 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu compact type tm operating modes the compact t ype tm can operate in one of three operating modes, compare match output mode, pwm mo de o r t imer/counter mo de. t he o perating m ode i s se lected u sing t he t nm1 a nd t nm0 bits in the tmnc1 register. compare match output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register , should be set to "00" respectively . in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare matc h from comparator a and a compare match from comparator p . when the tncclr bit is low , there are two ways in which the counter can be cleared. one is when a c ompare m atch o ccurs f rom c omparator p , t he o ther i s wh en t he c crp b its a re a ll z ero wh ich allows the counter to overfow . here both tnaf and tnpf interrupt request fags for the comparator a and comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt request fag will be generated. if the ccra bits are all zero, the counter will overfow when its reac hes its maximum 10-bit, 3ff hex, or 16-bit, ffff hex ,value, however here the tnaf interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the tm output pin will change state. the tm output pin condition however only changes state when a tnaf interrupt request fag is ge nerated a fter a c ompare m atch oc curs from co mparator a. t he t npf i nterrupt re quest fl ag, generated from a compare match occurs from comparator p , will have no ef fect on the tm output pin. t he wa y i n wh ich t he t m o utput p in c hanges st ate a re d etermined b y t he c ondition o f t he tnio1 and tnio0 bits in the tmnc1 register . the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from com parator a. t he i nitial c ondition of t he t m out put pi n, whi ch i s se tup a fter t he tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place.
rev. 1.00 70 ?a? 1?? ?01? rev. 1.00 71 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu counter value ccrp ccra tnon tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf t? o / p pin time ccrp =0 ccrp > 0 counter overflow ccrp > 0 counter cleared b? ccrp value pause resume stop counter restart tncclr = 0 ; tn? [1:0 ] = 00 output pin set to initial level low if tnoc =0 output toggle with tnaf flag note tnio [1:0 ] = 10 active high output select here tnio [1:0 ] = 11 toggle output select output not affected b? tnaf flag. remains high until reset b? tnon bit output pin reset to initial value output controlled b? other pin - shared function output inverts when tnpol is high 0x? ff or 0 xffff compare match output mode C tncclr=0 note: 1. w ith tncclr=0, a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. n=0, 1
rev. 1.00 7 ? ? a ? 1 ?? ? 01 ? rev. 1.00 7? ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu ccrp ccra 0x ? ff or 0xffff ccra = 0 counter overflows ccrp int. flag tnpf ccra int. flag tnaf ccra > 0 counter cleared b ? ccra value t ? o/p pin tnon bit pause counter reset output pin reset to initial value output pin set to initial level low if tnoc = 0 output toggle with tnaf flag here tnio1 ? tnio0 = 11 toggle output select now tnio1 ? tnio0 = 10 active high output select tnpau bit resume stop time tnpf not generated no tnaf flag generated on ccra overflow output does not change ccra = 0 output inverts when tnpol is high tnpol bit tncclr = 1; tn ? [1 ? 0] = 00 output controlled b ? other pin - shared function output not affected b ? tnaf flag remains high until reset b ? tnon bit counter value compare match output mode C tncclr=1 note: 1. w ith tncclr=1, a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf fag is not generated when tncclr=1 5. n=0, 1
rev. 1.00 7? ?a? 1?? ?01? rev. 1.00 7 ? ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 1 1 respectively . the t imer/counter m ode operates in an identical w ay to the compare m atch o utput m ode generating the same interrupt fags. the exception is that in the t imer/counter mode the tm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively . the pwm functio n within the tm is useful for applications which require functions such as motor control, h eating c ontrol, i llumination c ontrol e tc. b y p roviding a si gnal o f f ixed f requency b ut of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform i s e xtremely fl exible. in t he pwm m ode, t he t ncclr bi t ha s no e ffect on t he pwm operation. bot h of t he ccra a nd ccrp re gisters a re use d t o ge nerate t he pw m wave form, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the tndpx bit in the tmnc1 register . the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. 10-bit ctm, pwm mode, edge-aligned mode, t0dpx=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period 1 ? 8 ? 56 ? 84 51 ? 640 768 896 10 ? 4 dut ? ccra if f sys =16mhz, tm clock source is f sys /4, ccrp=100b and ccra=128, the ctm pwm output frequency=(f sys /4)/512=f sys /2048=7.8125 khz, duty=128/512=25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. 10-bit ctm, pwm mode, edge-aligned mode, t0dpx=1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period ccra dut ? 1 ? 8 ? 56 ? 84 51 ? 640 768 896 10 ? 4 the pw m o utput p eriod i s d etermined b y t he c cra r egister v alue t ogether wi th t he t m c lock while the pwm duty cycle is defned by the ccrp register value.
rev. 1.00 74 ? a ? 1 ?? ? 01 ? rev. 1.00 75 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu 16-bit ctm, pwm mode, edge-aligned mode, t1dpx=0 ccrp 1~255 0 period ccrp ? 56 655 ? 6 dut ? ccra if f sys =16mhz, tm clock source is f sys /4, ccrp=2 and ccra=128, the ct m pw m out put fre quency=(f sys /4)/(2256)=f sys /2048=7.8125 khz , dut y=128/ (2256)=25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. 16-bit ctm, pwm mode, edge-aligned mode, t1dpx=1 ccrp 1~255 0 period ccra dut ? ccrp ? 56 655 ? 6 the pw m o utput p eriod i s d etermined b y t he c cra r egister v alue t ogether wi th t he t m c lock while the pwm duty cycle is defned by the (ccrp256) except when the ccrp value is equal to 0. counter value ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf t? o/p pin (tnoc=1) time counter cleared b? ccrp pause resume counter stop if tnon bit low counter reset when tnon returns high tndpx = 0; tn? [1:0] = 10 pw? dut? c?cle set b? ccra pw? resumes operation output controlled b? other pin-shared function output inverts when tnpol = 1 pw? period set b? ccrp t? o/p pin (tnoc=0) pwm mode C tndpx=0 note: 1. here tndpx=0 C counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues even when tnio [1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation 5. n=0, 1
rev. 1.00 74 ?a? 1?? ?01? rev. 1.00 75 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu counter value ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf t? o/p pin (tnoc=1) time counter cleared b? ccra pause resume counter stop if tnon bit low counter reset when tnon returns high tndpx = 1; tn? [1:0] = 10 pw? dut? c?cle set b? ccrp pw? resumes operation output controlled b? other pin-shared function output inverts when tnpol = 1 pw? period set b? ccra t? o/p pin (tnoc=0) pwm mode C tndpx=1 note: 1. here tndpx=1 C counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues even when tnio [1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation 5. n=0, 1 buzzer control buzzer ht 66f? 5??0 10 -bit ct? t?0 the 10-bit ctm can drive an external buzzer using its pwm mode to provide volume control.
rev. 1.00 76 ? a ? 1 ?? ? 01 ? rev. 1.00 77 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu standard type tm C stm the standard t ype tm contains fve operating modes, which are compare match output, t imer/ event counter , capture input, single pulse output and pwm output modes. the standard tm can also be controlled with an external input pin and can drive two external output pins. name tm no. tm input pin tm output pin 10 -bit st ? ? tck ? tp ? _0 ? tp ? _1                         
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       ?  ?  ?             ? ??? ?? ? ??? ? ? ? ? ? ? ?? ? ? ?  ? ?    ? ?  ? ? ? ? ? ?  ?  standard type tm block diagram (n=2) the 10-bit stm can capture the noise fliter dat_out signal time between the raising edge and falling edge. 10 bit st? ( t? ?) ci ns 0 original tp ? capture in ( ex . tp ?_ 0 or tp ?_1) capture in 1 noise filter dat _ out tm2 in capture mode signal select standard tm operation at its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. t here a re a lso t wo i nternal c omparators wi th t he na mes, com parator a a nd com parator p. t hese c omparators wi ll c ompare t he v alue i n t he c ounter wi th c crp a nd c cra r egisters. t he ccrp is 3-bits wide whose value is compared with the highest 3 bits in the counter while the ccra is the 10 bits and therefore compares with all counter bits. the onl y way of changing the value of the 10-bit counte r using the appl ication program , is to clear the counter by changing the t2on bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when thes e conditions occur , a tm interrupt s ignal w ill als o us ually be generated. the s tandard type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers.
rev. 1.00 76 ?a? 1?? ?01? rev. 1.00 77 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu standard type tm register description overall operation of the standard tm is controlled using a series of registers. a read only register pair e xists t o st ore t he i nternal c ounter 10 -bit va lue, whi le a re ad/write re gister pa ir e xists t o st ore the internal 10-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three ccrp bits. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t ?? c0 t ? pau t ? ck ? t ? ck1 t ? ck0 t ? on t ? rp ? t ? pr1 t ? pr0 t ?? c1 t ?? 1 t ?? 0 t ? io1 t ? io0 t ? oc t ? pol t ? dpx t ? cclr t ?? dl d7 d6 d5 d4 d ? d ? d1 d0 t ?? dh d9 d8 t ?? al d7 d6 d5 d4 d ? d ? d1 d0 t ?? ah d9 d8 10-bit standard tm register list tm2c0 register C 10-bit stm bit 7 6 5 4 3 2 1 0 name t ? pau t ? ck ? t ? ck1 t ? ck0 t ? on t ? rp ? t ? pr1 t ? pr0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t2pau: tm2 counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t2ck2~t2ck0: select tm2 counter clock 000: f /4 001: f 010: f h /16 011: f h /64 100: f tbc 101: f tbc 110: tck2 rising edge clock 111: tck2 falling edge clock these three bits are used to select the clock source for the tm2. t he external pin clock source can be chosen to be active on the rising or falling edge. the cloc k source f is the system clock, while f h and f are other internal clocks, the detai ls of which can be found in the oscillator section. bit 3 t2on: tm2 counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tm2. setting the bit high enables the counter to run, clearing the bit disables the tm2. clearing this bit to zero will stop the counter from counting and turn of f the tm2 which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value until the bit returns high again. if the tm2 is in the compare match output mode then the tm2 output pin will be reset to its initial condition, as specifed by the t2oc bit, when the t2on bit changes from low to high.
rev. 1.00 78 ? a ? 1 ?? ? 01 ? rev. 1.00 79 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu bit 2~0 t2rp2~t2rp0: tm2 ccrp 3-bit register, compared with the tm2 counter bit 9~bit 7 comparator p match period 000: 1024 tm2 clocks 001: 128 tm2 clocks 010: 256 tm2 clocks 011: 384 tm2 clocks 100: 512 tm2 clocks 101: 640 tm2 clocks 110: 768 tm2 clocks 111: 896 tm2 clocks these three bits are used to setup the value on the internal ccrp 3-bit register , which are then compared with the internal counter s highest three bits. the result of this comparison c an be se lected t o c lear t he i nternal c ounter i f t he t 2cclr bi t i s se t t o zero. set ting t he t 2cclr bi t t o z ero e nsures t hat a c ompare m atch wi th t he ccrp values will reset the internal counter . as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing a ll t hree bi ts t o z ero i s i n e ffect a llowing t he c ounter t o ove rflow a t i ts maximum value tm2c1 register C 10-bit stm bit 7 6 5 4 3 2 1 0 name t ?? 1 t ?? 0 t ? io1 t ? io0 t ? oc t ? pol t ? dpx t ? cclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 t2m1~t2m0: select tm2 operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: t imer/counter mode these bits setup the required operating mode for the tm. t o ensure reliable operation the tm should be switched of f before any changes are made to the t2m1 and t2m0 bits. in the t imer/counter mode, the tm output pin control must be disabled. bit 5~4 t2io1~t2io0: select tp2_0, tp2_1 output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm mode /single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp 2 _0, tp 2_1 01: input capture at falling edge of tp 2 _0, tp 2_1 10: input capture at falling/rising edge of tp 2 _0, tp 2_1 11: input capture disabled timer/counter mode unused these two bits are used to determine how the tm2 output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm2 is running.
rev. 1.00 78 ?a? 1?? ?01? rev. 1.00 79 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu in t he com pare ma tch out put mode , t he t 2io1 a nd t 2io0 bi ts de termine how t he tm2 output pin changes state when a compare match occurs from the comparator a. the t m2 ou tput pi n c an be se tup t o swi tch hi gh, swi tch l ow or t o t oggle i ts pr esent state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm2 output pin should be setup using the t2oc bit in the tm2c1 register . note that the output level requested by the t2io1 and t2io0 bits must be dif ferent from the initial value setup using the t2oc bit otherwise no change will occur on the tm2 output pin when a compare match occurs. after the tm2 output pin changes state it can be reset to its initial level by changing the level of the t2on bit from low to high. in the pwm mode, the t2io1 and t2io0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function i s m odified b y c hanging t hese t wo b its. i t i s n ecessary t o o nly c hange t he values of t he t 2io1 a nd t 2io0 bi ts onl y a fter t he t m2 ha s be en swi tched of f. unpredictable pwm outputs will occur if the t 2io1 and t 2io0 bits are changed when the tm is running. bit 3 t2oc: tp2_0, tp2_1 output control bit compare match output mode 0: initial low 1: initial high pwm mode / /single pulse output mode 0: active low 1: active high this is the output control bit for the tm2 output pin. its operation depends upon whether tm2 is being used in the compare match output mode or in the pwm mode / single pulse output mode. it has no ef fect if the tm2 is in the t imer/counter mode. in the compare match output mode it determines the logic level of he tm2 output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t2pol: tp2_0, tp2_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp2_0 or tp2_1 output pin. when the bit is set high the tm2 output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm2 is in the t imer/counter mode. bit 1 t2dpx: tm2 pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 t2cclr: select tm2 counter clear condition 0: tm2 comparator p match 1: tm2 comparator a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he compact t m2 c ontains t wo c omparators, c omparator a a nd c omparator p , e ither of which can be selected to clear the internal counter . w ith the t2cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the t2cclr bit is not used in the pwm mode.
rev. 1.00 80 ? a ? 1 ?? ? 01 ? rev. 1.00 81 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu tm2dl register C 10-bit stm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm2dl: tm2 counter low byte register bit 7~bit 0 tm2 10-bit counter bit 7~bit 0 tm2dh register C 10-bit stm bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tm2dh: tm2 counter high byte register bit 1~bit 0 tm2 10-bit counter bit 9~bit 8 tm2al register C 10-bit stm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm2al: tm2 ccra low byte register bit 7~bit 0 tm2 10-bit ccra bit 7~bit 0 tm2ah register C 10-bit stm bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tm2 ah: tm2 ccra high byte register bit 1~bit 0 tm2 10-bit ccra bit 9~bit 8
rev. 1.00 80 ?a? 1?? ?01? rev. 1.00 81 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu standard type tm operating modes the standard t ype tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or t imer/counter mode. the operating mode is selected using the t2m1 and t2m0 bits in the tm2c1 register. compare output mode to select this mode, bits t2m1 and t2m0 in the tm2c1 register , should be set to 00 respectively . in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare matc h from comparator a and a compare match from comparator p . when the t2cclr bit is low , there are two ways in which the counter can be cleared. one is when a c ompare m atch f rom c omparator p , t he o ther i s wh en t he c crp b its a re a ll z ero wh ich a llows the c ounter t o ove rfow. he re bot h t 2af a nd t 2pf i nterrupt re quest fa gs for com parator a a nd comparator p respectively, will both be generated. if the t2cclr bit in the tm2c1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the t2af interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when t2cclr i s h igh n o t 2pf i nterrupt r equest fa g wi ll b e g enerated. i n t he c ompare ma tch ou tput mode, the ccra can not be set to "0". as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when a t2af interrupt request fag is ge nerated a fter a c ompare m atch oc curs from co mparator a. t he t 2pf i nterrupt re quest fl ag, generated from a compare match occurs from comparator p , will have no ef fect on the tm output pin. t he wa y i n wh ich t he t m o utput p in c hanges st ate a re d etermined b y t he c ondition o f t he t2io1 and t2io0 bits in the tm2c1 register . the tm output pin can be selected using the t2io1 and t2io0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from com parator a. t he i nitial c ondition of t he t m out put pi n, whi ch i s se tup a fter t he t2on bit changes from low to high, is setup using the t2oc bit. note that if the t2io1 and t2io0 bits are zero then no pin change will take place.
rev. 1.00 8 ? ? a ? 1 ?? ? 01 ? rev. 1.00 8? ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu ccra ccrp 0x?ff counter overflow ccra int. flag tnaf ccrp int. flag tnpf ccrp > 0 counter cleared b? ccrp value t? o/p pin tnon pause counter reset output pin set to initial level low if tnoc = 0 output toggle with tnaf flag here tnio [1:0] = 11 toggle output select now tnio [1:0] = 10 active high output select output not affected b? tnaf flag. remains high until reset b? tnon bit tncclr = 0; tn? [1:0] = 00 tnpau resume stop time ccrp > 0 ccrp = 0 tnapol output pin reset to initial value output inverts when tnpol is high output controlled b? other pin - shared function counter value compare match output mode C tncclr=0 note: 1. w ith tncclr = 0 a comparator p match will clear the counter 2. the tm output pin controlled only by the tnaf fag 3. the output pin reset to initial state by a tnon bit rising edge 4. n = 2
rev. 1.00 8? ?a? 1?? ?01? rev. 1.00 8 ? ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu ccrp ccra 0x?ff ccra = 0 counter overflows ccrp int. flag tnpf ccra int. flag tnaf ccra > 0 counter cleared b? ccra value t? o/p pin tnon pause counter reset output pin reset to initial value output pin set to initial level low if tnoc = 0 output toggle with tnaf flag here tnio [1:0] = 11 toggle output select now tnio [1:0] = 10 active high output select tnpau resume stop time tnpf not generated no tnaf flag generated on ccra overflow output does not change ccra = 0 output inverts when tnpol is high tnpol tncclr = 1; tn? [1:0] = 00 output controlled b? other pin - shared function output not affected b? tnaf flag remains high until reset b? tnon bit counter value compare match output mode C tncclr=1 note: 1. w ith tncclr = 1 a comparator a match will clear the counter 2. the tm output pin controlled only by the tnaf fag 3. the output pin reset to initial state by a tnon rising edge 4. the tnpf fags is not generated when tncclr = 1 5. n = 2
rev. 1.00 84 ? a ? 1 ?? ? 01 ? rev. 1.00 85 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu timer/counter mode to select this mode, bits t2m1 and t2m0 in the tm2c1 register should be set to 1 1 respectively . the t imer/counter m ode operates in an identical w ay to the compare m atch o utput m ode generating the same interrupt fags. the exception is that in the t imer/counter mode the tm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to se lect t his mode , bit s t 2m1 and t 2m0 i n t he t m2c1 regi ster should be se t t o 10 respe ctively and also the t2io1 and t2io0 bits should be set to 10 respectively . the pwm function within the tm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fxed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform i s e xtremely fl exible. in t he pw m m ode, t he t 2cclr bi t ha s no e ffect a s t he pw m period. both of the ccraand ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the t2dpx bit in the tm2c1 register. the pw m wa veform f requency a nd d uty c ycle c an t herefore b e c ontrolled b y t he v alues i n t he ccra and ccrp registers. an interrupt flag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the t2oc bit in the tm2c1 register is used to select the required polarity of the pwm waveform while the two t2io1 and t2io0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the t2pol bit is used to reverse the polarity of the pwm output waveform. 10-bit stm, pwm mode, edge-aligned mode, t2dpx=0 ccrp 001 010 011 100 101 110 111 000 period 1 ? 8 ? 56 ? 84 51 ? 640 768 896 10 ? 4 dut ? ccra if f sys = 4mhz, tm clock source is f sys , ccrp = 2 and ccra =128, the stm pwm output frequency = f sys / (2256) = f sys /512 = 7.8125 khz, duty = 128/(2256) = 25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. 10-bit stm, pwm mode, edge-aligned mode, t2dpx=1 ccrp 001 010 011 100 101 110 111 000 period ccra dut ? 1 ? 8 ? 56 ? 84 51 ? 640 768 896 10 ? 4 the pw m o utput p eriod i s d etermined b y t he c cra r egister v alue t ogether wi th t he t m c lock while the pwm duty cycle is defned by the ccrp register value.
rev. 1.00 84 ?a? 1?? ?01? rev. 1.00 85 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu counter value ccrp ccra tnon tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf t? o / p pin ( tnoc =1) time counter cleared b? ccrp pause resume counter stop if tnon bit low counter reset when tnon returns high tndpx = 0 ; tn? [1:0 ] = 10 pw? dut? c?cle set b? ccra pw? resumes operation output controlled b? other pin - shared function output inverts when tnpol = 1 pw? period set b? ccrp t? o / p pin ( tnoc =0) pwm mode C tndpx=0 note: 1. here tndpx = 0 - counter cleared by ccrp 2. a counter clear sets pwm period 3. the internal pwm function continues running even when tnio[1:0] = 00 or 01 4. the tncclr bit has no infuence on pwm operation 5. n = 2
rev. 1.00 86 ? a ? 1 ?? ? 01 ? rev. 1.00 87 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu counter value ccrp ccra tnon tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf t? o / p pin ( tnoc =1) time counter cleared b? ccra pause resume counter stop if tnon bit low counter reset when tnon returns high tndpx = 1 ; tn? [1:0 ] = 10 pw? dut? c?cle set b? ccrp pw? resumes operation output controlled b? other pin - shared function output inverts when tnpol = 1 pw? period set b? ccra t? o / p pin ( tnoc =0) pwm mode C tndpx=1 note: 1. here tndpx = 1 - counter cleared by ccra 2. a counter clear sets pwm period 3. the internal pwm function continues even when tnio[1:0] = 00 or 01 4. the tncclr bit has no infuence on pwm operation 5. n = 2
rev. 1.00 86 ?a? 1?? ?01? rev. 1.00 87 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu single pulse mode to se lect t his mode , bit s t 2m1 and t 2m0 i n t he t m2c1 regi ster should be se t t o 10 respe ctively and also the t2io1 and t2io0 bits should be set to 1 1 respectively . the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse output lead ing edge is a low to high transition of the t2on bit, which can be implemented using the application program. however in the single pulse mode, the t2on bit can also be made to automatically change from low to high using the external tck2 pin, which will in turn initiate the single pulse output. when the t2on bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the t2on bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the t2on bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a.            
                         
            
?  ? ?     ?   ? ? ?   ?      ? ? ?   single pulse generation (n=2) however a compare match from comparator a will also automatically clear the t2on bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate a tm interrupt. the counter can only be reset back to zero when the t2on bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the t2cclr and t2dpx bits are not used in this mode. capture input mode to s elect this mode bits t2m1 and t2m0 in the tm 2c1 regis ter s hould be s et to 01 respectively . this mode enables external s ignals to capture and s tore the pres ent value of the internal counter and can therefore be used for applic ations such as pulse width measurements. the external signal is supplied on the tp2_0 or tp2_1 pin, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the t2io1 and t2io0 bits in the tm 2c1 regis ter. the counter is s tarted w hen the t2o n bit changes from low to high which is initiated using the application program. when the required edge transition appears on the tp2_0 or tp2_1 pin the present value in the counter will be latched into the ccra registers and a tm interrupt generated. irrespective of what events occur on the tp2_0 or tp2_1 pin the counter will continue to free run until the t2on bit changes from high to low . when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p , a tm interrupt will also be generated. counting the number of ov erflow i nterrupt si gnals fro m t he cc rp c an be a use ful m ethod i n m easuring l ong pulse widths. the t2io1 and t2io0 bits can select the active trigger edge on the tp2_0 or tp2_1 pin to be a ris ing edge, falling edge or both edge types . if the tnio 1 and t2io 0 bits are both s et high, then no capture operation will take place irrespective of what happens on the tp2_0 or tp2_1 pin, however it must be noted that the counter will continue to run. as the tp2_0 or tp2_1 pin is pin shared with other functions, care must be taken if the tm is in the input capture mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture oper ation to be executed. the t2cclr and t2dpx bits are not used in this mode.
rev. 1.00 88 ? a ? 1 ?? ? 01 ? rev. 1.00 89 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu counter value ccrp ccra tnon tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf t? o / p pin ( tnoc =1) time counter stopped b? ccra pause resume counter stops b? software counter reset when tnon returns high tn? [1:0 ] = 10 ; tnio [1:0 ] = 11 pulse width set b? ccra output inverts when tnpol = 1 no ccrp interrupts generated t? o / p pin ( tnoc =0) tckn pin software trigger cleared b? ccra match tckn pin trigger auto . set b? tckn pin software trigger software clear software trigger software trigger single pulse mode note: 1. counter stopped by ccra match 2. ccrp is not used 3. the pulse is triggered by the tckn pin or setting the tnon bit high 4. a tckn pin active edge will automatically set the tnon bit high 5. in the single pulse mode, tnio [1:0] must be set to "11" and can not be changed. 6. n = 2
rev. 1.00 88 ?a? 1?? ?01? rev. 1.00 89 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu counter value yy ccrp tnon tnpau ccrp int . flag tnpf ccra int . flag tnaf ccra value time counter cleared b? ccrp pause resume counter reset tn? [1:0 ] = 01 t? capture pin tpn _x xx counter stop tnio [1:0 ] value xx yy xx yy active edge active edge active edge 00 C rising edge 01 C falling edge 10 C both edges 11 C disable capture capture input mode note: 1. tnm[1:0] = 01 and active edge set by the tnio[1:0] bits 2. a tm capture input pin active edge transfers the counter value to ccra 3. the tncclr bit is not used 4. no output function - tnoc and tnpol bits are not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero. 6. n = 2
rev. 1.00 90 ? a ? 1 ?? ? 01 ? rev. 1.00 91 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu capture timer module C captm the capture t imer module is a timing unit specifically used for motor control purposes. the captm is controlled by a program selectable clock source and by three interrupt sources from the motor positioning hall sensors. capture timer overview at the core of the capture t imer is a 16-bit count-up counter which is driven by a user selectable internal clock source which is some multiple of the system clock or by the pwm. there is also an internal comparator which compares the value of this 16-bit counter with a pre-programmed 16- bit value stored in two registers. there are two basic modes of operation, a compare mode and a ca pture mode , e ach of whi ch c an be use d t o re set t he i nternal c ounter. w hen a c ompare m atch situation is reache d a signal will be generated to reset the internal counter . the counter can also be cleared when a capture trigger is generated by the three external sources, h1, h2 and h3 . rising / falling / double edge detector noise filter x? rising / falling / double edge detector compare register capt?ah / capt?al compare capt?ch / capt?cl clear capture counter clr capt? _ over capt? _ cmp h1 h? h? caps 1/ caps 0 16 - bit capt? clk captck [?:0] pw?o f sys /? f sys / 1?8 f sys / 64 ha _ int hb _ int hc _ int ha hb hc capture timer block diagram capture timer register description overall ope ration of t he ca pture t imer i s c ontrolled usi ng e ight re gisters. a re ad onl y re gister pa ir exists to store the internal counter 16-bit value, while a read/write register pair exists to store the internal 16-bit compare value. an additional read only register pair is used to store the capture value. the remaining two registers are control registers which setup the different operating and control modes. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 captc0 captpau captck ? captck1 captck0 capton caps1 caps0 captc1 capeg1 capeg0 capen capnft capnfs capfil capclr ca ? clr capt ? dl d7 d6 d5 d4 d ? d ? d1 d0 capt ? dh d15 d14 d1 ? d1 ? d11 d10 d9 d8 capt ? al d7 d6 d5 d4 d ? d ? d1 d0 capt ? ah d15 d14 d1 ? d1 ? d11 d10 d9 d8 capt ? cl d7 d6 d5 d4 d ? d ? d1 d0 capt ? ch d15 d14 d1 ? d1 ? d11 d10 d9 d8 capture timer register list
rev. 1.00 90 ?a? 1?? ?01? rev. 1.00 91 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu captc0 register bit 7 6 5 4 3 2 1 0 name captpau captck ? captck1 captck0 capton caps1 caps0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 captpau: captm counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the captm will remain power up a nd c ontinue t o c onsume po wer. t he c ounter wi ll re tain i ts re sidual va lue whe n this bit changes from low to high and res ume counting from this value w hen the bit changes to a low value again . bit 6~4 captck2~captck0: select captm counter clock 000: pwmo 001: f h /2 010: f h /4 011: f h /8 100: f h /16 101: f h /32 110: f h /64 111: f h /128 these three bits are used to select the clock source for the captm. the clock source h is the high speed system oscillator. bit 3 capton: captm counter on/off control 0: off 1: on this bit controls the overall on/of f function of the captm. setting the bit high enables t he c ounter t o run, c learing t he bi t di sables t he capt m. cl earing t his bi t t o zero will stop the counter from counting and turn of f the captm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value. bit 2 unimplemented, read as "0" bit 1~0 caps1~caps0: capture source select 00: h1 01: h2 10: h3 11: ctin
rev. 1.00 9 ? ? a ? 1 ?? ? 01 ? rev. 1.00 9? ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu captc1 register bit 7 6 5 4 3 2 1 0 name capeg1 capeg0 capen capnft capnfs capfil capclr ca ? clr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 capeg1~capeg0: defnes captm capture active edge 00: disabled captm capture 01: rising edge capture 10: falling edge capture 11: dual edge capture bit 5 capen: captm capture input control 0: disable 1: enable this bit enables/disables the captm capture input source. bit 4 capnft: defnes captm noise filter sample times 0: t wice 1: 4 times the captm noise filter circuit requires sampling twice or 4 times continuously , when they are all the same, the signal will be acknowledged. the sample time is decided by capnfs. bit 3 capnfs: captm noise filter clock source select 0: t 1: 4t the clock source for capture t imer module counter is provided by f or f sys /4. bit 2 capfil: captm capture input flter control 0: disable 1: enable this bit enables/disables the captm capture input flter. bit 1 capclr: captm counter capture auto-reset control 0: disable 1: enable this bi t e nables/disables t he a utomatic re set of t he c ounter whe n t he va lue i n captmdl a nd c aptmdh h ave b een t ransferred i nto t he c apture r egisters captmcl and captmch. bit 0 camclr: captm counter compare match auto-reset control 0: disable 1: enable this bit enables/disables the automatic reset of the counter when a compare match has occurred. captmdl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 captmdl: captm counter low byte register bit 7~bit 0 captm 16-bit counter bit 7 ~ bit 0
rev. 1.00 9? ?a? 1?? ?01? rev. 1.00 9 ? ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu captmdh register bit 7 6 5 4 3 2 1 0 name d15 d14 d1 ? d1 ? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 captmdh: captm counter high byte register bit 7~bit 0 captm 16-bit counter bit 15 ~ bit 8. captmal register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 captmal: captm compare low byte register bit 7~bit 0 captm 16-bit compare register bit 7~bit 0. captmah register bit 7 6 5 4 3 2 1 0 name d15 d14 d1 ? d1 ? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 captmah: captm compare high byte register bit 7~bit 0 captm 16-bit compare register bit 15~bit 8. captmcl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por x x x x x x x x "x"unknown bit 7~0 captmcl: captm capture low byte register bit 7~bit 0 captm 16-bit capture register bit 7~bit 0 captmch register bit 7 6 5 4 3 2 1 0 name d15 d14 d1 ? d1 ? d11 d10 d9 d8 r/w r r r r r r r r por x x x x x x x x "x"unknown bit 7~0 captmch: captm capture high byte register bit 7~bit 0 captm 16-bit capture register bit 15~bit 8.
rev. 1.00 94 ? a ? 1 ?? ? 01 ? rev. 1.00 95 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu capture timer operation the capture t imer is used to detec t and measure input signal pulse widths and a periods. it can be used in both a capture or compare mode. the timer inputs are the four capture inputs h1, h2 and h3. each of these capture inputs has its own edge detector selection, to choose between high, low or both edge trigger types. the capt on bit is used to control the overall capture t imer enable/disable function. disabling the capture module when not used will reduce the device power consumption. additionally the capture input control is enabled/disabled using the capen control bit. the trigger edge options are setup using the capeg1 and capeg0 bits, to select either positive edge, negative edge or both edges. the time r also includes a noise filter which is used to flter out unwanted glitches or pulses on the h1, h2, h3 and nfin input pins. this function is enabled using the capfil bit. if the noise flter is enabled, the captu re input signals must be sampled either 2 or 4 times, in order to recognize an edge as a valid capture event. the sampling 2 or 4 time units are based o eith er t sys or 4 t sys determined using the capnfs bit. i/p o/p noise filter sampling noise filter with capnft and catnfs = 0 capture mode operation the capture timer module contains 2 capture registers, captmcl and captmch, which are used to store the present value in the counter . when the capture module is enabled, then each time an external pin receiv es a valid trigger signal, the content of the free running 16-bit counter , which is contained i n t he capt mdl a nd capt mdh re gisters, wil l be c aptured i nto t he c apture re gisters, captmcl a nd capt mch. w hen t his oc curs, t he capof i nterrupt fl ag bi t i n t he i nterrupt control re gister wi ll be se t. if t his i nterrupt i s e nabled by se tting t he i nterrupt e nable bi t, capoe , high, an interrupt will be generated. if the capclr bit is set high, then the 16-bit counter will be automatically reset after a capture event occurs. compare mode operation when the timer is used in the compare mode, the captmal and captmah registers are used to store the 16-bit compare value. when the free running value of the count-up 16-bit counter reaches a va lue e qual t o t he prog rammed va lues i n t hese c ompare re gisters, t he capc f i nterrupt fa g wi ll be set which will generate an interr upt if its related interrupt enable bit is set. if the camclr bit is se t h igh, t hen t he c ounter wi ll b e r eset t o z ero a utomatically wh en a c ompare m atch c ondition occurs. the rotor speed or a stalled motor condition can be detected by setting the compare registers to compa re the captured signal edge transition time. if a rotor stall condition occurs, then a compare interrupt will be generated, after which the pwm motor drive circuit can be shut down to prevent a motor burn out situation.
rev. 1.00 94 ?a? 1?? ?01? rev. 1.00 95 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu noise filter the exter nal nfin pin is connected to an internal flter to reduce the possibility of unwanted event counting events or inaccurate pulse width measurements due to adverse noise or spikes on the nfin input signal and then output to stm capture circuit. in order to ensure that the motor control circuit works normally. the noise flter circuit is a n i/o fltering sur ge compare which can flter micro-second grade sharp- noise. antinoise pulse width maximum: (nf_vih[4:0]-nf_vil[4:0])5s, (nf_vih[4:0]-nf_ vil[4:0])>1 dat _ in dat _ out noise filter dat _ in dat _ out nf _ vih [4:0] nf _ vil [4:0] st? noise filter registers description nf_vih register bit 7 6 5 4 3 2 1 0 name nf_byps cins d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 1 0 0 1 bit 7 bypass noise filter enable 0: disable 1: enable, dat_out=dat_in bit 6 stm capture source selection 0: no select noise filter dat_out(remain s the original stm path ) 1: select noise filter dat_out bit 5 unimplemented, read as "0" bit 4~0 nf_vih register bit 4~bit 0
rev. 1.00 96 ? a ? 1 ?? ? 01 ? rev. 1.00 97 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu nf_vil register bit 7 6 5 4 3 2 1 0 name nfis1 nfis0 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 1 0 1 0 bit 7~6 nfis1~nfis0: n n interrupt edge control 00: disable 01: rising edge trigger 10: falling edge trigger 11: dual edge trigger bit 5 unimplement, read as "0" bit 4~0 nf_vil register bit 4~bit0 comparators four i ndependent a nalog c omparators a re c ontained wi thin t hese de vices. t hese func tions of fer fexibility via their register controlled features such as power -down, polarity select, hysteresis etc. in sharing their pins with normal i/o pins the comparators do not waste precious i/o pins if there functions are otherwise unused. comparators block diagram c?p c?x c?p c?x + - comparator 1 c1x c0x c1p opa output pin share control dac output c1n + - comparator 0 + - comparator ? + - comparator ?
rev. 1.00 96 ?a? 1?? ?01? rev. 1.00 97 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu comparator operation the d evice c ontains f our c omparator f unctions wh ich a re u sed t o c ompare t wo a nalog v oltages and provide an output based on their dif ference. additional comparator functions include, output polarity, h ysteresis f unctions a nd p ower d own c ontrol. an y p ull-high r esistors c onnected t o t he shared comparato r input pins will be automatically disconnected when the comparator pin-share is enabled. as the comparator inputs approach their switching level, some spurious output signals may be generated on the comparator output due to the slow rising or falling nature of the input signals. this can be minimised by selecting the hysteresis function will apply a small amount of positive feedback to the comparator . ideally the comparator should switch at the point where the positive and negative inputs signals are at the same voltage level, however , unavoidable input of fsets introduce some uncertainties here. the hysteresis function, if enabled, also increases the switching offset value. cpc register bit 7 6 5 4 3 2 1 0 name c ? hyen c ? hyen c1hyen c0hyen c ? en c ? en c1en c0en r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 0 0 0 0 bit 7 c3hyen: comparator 3 hysteresis control 0: off 1: on this is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator , as specifed in the comparator electrical characteristics table. the positive feedback induced by hysteresis reduces the ef fect of spurious switching near the comparator threshold. bit 6 c2hyen: comparator 2 hysteresis control 0: off 1: on this is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator , as specifed in the comparator electrical characteristics table. the positive feedback induced by hysteresis reduces the ef fect of spurious switching near the comparator threshold. bit 5 c1hyen: comparator 1 hysteresis control 0: off 1: on this is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator , as specifed in the comparator electrical characteristics table. the positive feedback induced by hysteresis reduces the ef fect of spurious switching near the comparator threshold. bit 4 c0hyen: comparator 0 hysteresis control 0: off 1: on this is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator , as specifed in the comparator electrical characteristics table. the positive feedback induced by hysteresis reduces the ef fect of spurious switching near the comparator threshold. bit 3 c3en: comparator 3 on/off control 0: off 1: on this i s t he com parator on/ off c ontrol bi t. if t he bi t i s z ero t he c omparator wi ll be switched of f and no power consumed even if analog voltages are applied to its inputs. for power sensitive applications this bit should be cleared to zero if the comparator is not used or before the device enters the power-down mode.
rev. 1.00 98 ? a ? 1 ?? ? 01 ? rev. 1.00 99 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu bit 2 c2en: comparator 2 on/off control 0: off 1: on this i s t he com parator on/ off c ontrol bi t. if t he bi t i s z ero t he c omparator wi ll be switched of f and no power consumed even if analog voltages are applied to its inputs. for power sensitive applications this bit should be cleared to zero if the comparator is not used or before the device enters the power-down mode. bit 1 c1en: comparator 1 on/off control 0: off 1: on this i s t he com parator on/ off c ontrol bi t. if t he bi t i s z ero t he c omparator wi ll be switched of f and no power consumed even if analog voltages are applied to its inputs. for power sensitive applications this bit should be cleared to zero if the comparator is not used or before the device enters the power-down mode. bit 0 c0en: comparator 0 on/off control 0: off 1: on this i s t he com parator on/ off c ontrol bi t. if t he bi t i s z ero t he c omparator wi ll be switched of f and no power consumed even if analog voltages are applied to its inputs. for power sensitive applications this bit should be cleared to zero if the comparator is not used or before the device enters the power-down mode. analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however , to properly process these signals by a microcontroller , they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller , the need for external components is reduced signifcantly with the corresponding fol low-on be nefts of l ower c osts a nd re duced c omponent spa ce re quirements. t his device also includes some special a/d features for specifc use in motor control applications. a/d overview this device contains a -channel analog to digital converter , -channel can be directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into eithe r a 10-bit digital value. an additional channel is connected to the external current sense input pin, ap , via an internal operational amplifier for signal amplification, before being transferred to the a/d converter input. a set of what are known as high and low boundary registers, allow the a/d converter digital output value to be compared with upper and lower limit values and a corresponding interrupt to be generated. an additional delay function allows a delay to be inserted into the pwm triggered a/d conversion start process to reduce the possibility of erroneous analog value sampling when the output power transistors are switching large motor currents. input channels a/d channel select bits input pins 6+1 acs ? ~acs0 an0~an5 ? ap
rev. 1.00 98 ?a? 1?? ?01? rev. 1.00 99 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu the accompanying block diagram shows the overall internal structure of the a/d converter , together with its associated registers. adrh adrl adhvdh adhvdl adlvdh adlvdl adchve adclve high boundar? value low boundar? value comparison t?pe control bits int _ahl_ lim interrupt signal adc int _ad_eoc eocb bit compare converted value with upper and lower limits addl dela? register ?ux adsts bit start convert dela? time adstr bit pw? period interrupt signal pw? dut? interrupt signal ?ux pwis bit a/ d conversion start signal dlstr bit dela? on / off control programmable gain amplifier ap opavs0 opavs? gain control bits gain = x1/x5/x 10 /x ?0 acs ?~ acs 0 pb 0/ an ? pb ?/ an 5 pa 6/ an 0 pa 7/ an 1 pa 1/ an ? pb 1/ an 4 ad hl / lv trigger a/d converter structure a/d converter register description overall operation of the a/d converter is controlled using several registers. a read only register pair adrl/adrh exists to store the adc data 10-bit value. the adl vdl/adlvdh and adhvdl/ adhvdh registe rs are used to store the boundary limit values of the adc interrupt trigger while the addl re gister i s use d t o se tup t he st art c onversion de lay t ime. t he re maining re gisters a re control registers which setup the operating and control function of the a/d converter. register name bit 7 6 5 4 3 2 1 0 adrl d7 d6 d5 d4 d ? d ? d1 d0 adrh d9 d8 adcr0 adstr eocb adoff acs ? acs1 acs0 adcr1 adsts dlstr pwis adchve adclve adck ? adck1 adck0 adcr ? pwdis1 pwdis0 addl d7 d6 d5 d4 d ? d ? d1 d0 adlvdl d7 d6 d5 d4 d ? d ? d1 d0 adlvdh d9 d8 adhvdl d7 d6 d5 d4 d ? d ? d1 d0 adhvdh d9 d8 a/d converter register list
rev. 1.00 100 ? a ? 1 ?? ? 01 ? rev. 1.00 101 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu a/d converter data registers C adrl, adrh as t his d evice c ontains a n i nternal 1 0-bit a/ d c onverter, i t r equires t wo d ata r egisters t o st ore t he converted va lue. t hese a re a hi gh byt e re gister, kno wn a s adr h, a nd a l ow by te re gister, kno wn as adrl. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. adrl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por x x x x x x x x "x"unknown bit 7~0 a/d low byte register bit 7~bit 0 adrh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por x x "x"unknown bit 7~2 unimplemented, read as "0" bit 1~0 a/d high byte register bit 1~bit 0 a/d converter control registers C adcr0, adcr1, adcr2, addl to control the function and operation of the a/d converter , four control registers known as adcr0, adcr1 a nd adc r2 a re p rovided. t hese 8 -bit r egisters defne f unctions such a s t he se lection o f wh ich analog channel is connected to the internal a/d converter , the digitised data format, the a/d clock source as w ell as controlling the s tart function and monitoring the a /d converter end of convers ion status. t he acs2~acs0 bi ts i n t he adcr0 re gister de fne t he adc i nput c hannel num ber. as t he device contains only one actual analog to digital converter hardware circuit, each of the individual 6 analog inputs must be routed to the converter . it is the function of the acs2~acs0 bits to determine which analog channel input pins or ap pin is actually connected to the internal a/d converter. the addl register exists to store the adc delay start time. adcr0 register bit 7 6 5 4 3 2 1 0 name adstr eocb adoff acs ? acs1 acs0 r/w r/w r r/w r/w r/w r/w por 0 1 1 0 0 0 bit 7 adstr: start the a/d conversion 010 : start 01: reset the a/d converter and set eocb to "1" this bit is used to initiate an a/ d conversion process. the bit is normally low but if set high and then cleared low again, the a/d converter will initiate a conversion process. when the bit is set high the a/d converter will be reset. bit 6 eocb: end of a/d conversion fag 0: a/d conversion ended 1: a/d conversion in progress this read only fag is used to indicate when an a/d conversion process has completed. when the conversion process is running the bit will be high.
rev. 1.00 100 ?a? 1?? ?01? rev. 1.00 101 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu bit 5 adoff : adc module power on/off control bit 0: adc module power on 1: adc module power off this bit controls the power to the a/d internal function. this bit should be cleared to zero to enable the a/d converter . if the bit is set high then the a/d converter will be switched of f reducing the device power consumption. as the a/d converter will consume a limited amount of power , even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. note: 1. it is recommended to set adoff=1 before entering idle/sleep mode for saving power. 2. adoff=1 will power down the adc module. bit 4~3 unimplemented, read as "0" bit 2 ~ 0 acs2 ~ acs0 : select a/d channel 000: an0 001: an1 010: an2 011: an3 100: an4 101: an5 110: opa output 111: undefned these are the a/d channel select control bits. as there is only one internal hardware a/ d converter each of the six a/d inputs must be routed to the internal converter using these bits. adcr1 register bit 7 6 5 4 3 2 1 0 name adsts dlstr pwis adchve adclve adck ? adck1 adck0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 adsts: select adc trigger circuit 0: select adstr trigger circuit 1: select delay trigger circuit bit 6 dlstr: delay start function control 0: disable but need to set addl to "0" 1: enable but need to set addl to non zero value bit 5 pwis: select pwm module interrupt source 0: select pwm period interrupt 1: select pwm duty interrupt bit 4~3 adchve , adclve : select adc interrupt trigger source 00: adl vd[9:0] < adr[9:0] < adhvd[9:0] 01: adr[9:0] <= adl vd[9:0] 10:adr[9:0] >= adhvd[9:0] 11: adr[9:0] <= adl vd[9:0] or adr[9:0] >= adhvd[9:0] bit 2 ~ 0 adck2 ~ adck0 : select adc clock source 000: f 001: f /2 010: f /4 011: f /8 100: f /16 101: f /32 110: f /64 111: undefned these three bits are used to select the clock source for the a/d converter.
rev. 1.00 10 ? ? a ? 1 ?? ? 01 ? rev. 1.00 10? ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu adcr2 register bit 7 6 5 4 3 2 1 0 name pwdis1 pwdis0 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 pwdis1~pwdis0: pwis=1, select pwmn duty cycle interrupt trigger source 00: pwm0 01: pwm1 10: pwm2 11: reseved (select pwm2 duty cycle interrupt trigger source) addl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 adc delay-time register bit 7~bit 0 delay-time v alue (count by system clock) a/d converter boundary registers C adlvdl, adlvdh, adhvdl, adhvdh the device contains what are known as boundary registers to store fxed values for comparison with the a/d converter converted value stored in adrl and adrh. there are two pairs of registers, a high boundary pair , known as adhvdl and adhvdh and a low boundary pair known as adlvdl and adl vdh. adlvdl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 adc low boundary low byte register bit 7~bit 0 adlvdh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 adc low boundary high byte register bit 9~bit 8 adhvdl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 adc high boundary low byte register bit 7~bit 0
rev. 1.00 10? ?a? 1?? ?01? rev. 1.00 10 ? ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu adhvdh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 adc high boundary high byte register bit 9~bit 8 a/d operation there a re t wo wa ys t o i nitiate a n a/ d conve rter c onversion c ycle, se lected usi ng t he adst s bi t. the frst of these is to use the adstr bit in the adcr0 register used to start and reset the a/d converter. when the microcontroller program sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. when the adstr bit is brought from low to high but not low again, the eocb bit in the adcr0 register will be set high and the analog to digital converter will be reset. the sec ond me thod of ini tiating a conversion is to use t he pw m int errupt si gnal. thi s ca n be sourced from eithe r the pwm period or duty interrupt signal, selected using the pwis bit. if selects pwm duty interru pt signal, interrup t trigger source c an be selected by pwdis1 and pwdis2 in the adcr2 register . the dlstr bit can activate a delay function which inserts a delay time between the incoming pwm interrupt signal and the actual start of the a/d conversion process, with the actual tim e being setup using the addl register . the actual delay time is calculated by the register content multiplied by the system clock period. the delay between the pwm interrupt and the start of the a/d conversion is to reduce the possibility of erroneous analog samples being taken during the time of lar ge transient current switching by the motor drive transistors. note that if the dlstr bit select s no dela y the addl register must be cleared to zero and vice -versa if the delay is selected, then a non-zero value must be programmed into the addl register. the eocb bit i n t he adcr0 regi ster i s use d t o i ndicate whe n t he ana log t o di gital conve rsion process is complete. this bit will be automatically set to zero by the microcontroller after a conversion cycle has ended. in addition, the corresponding a/d interrupt request fag will be set in t he i nterrupt c ontrol r egister, a nd i f t he i nterrupts a re e nabled, a n a ppropriate i nternal i nterrupt signal wil l be generated. thi s a/ d i nternal int errupt si gnal wi ll direct the progra m flow t o t he associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the eocb bit in the adcr0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. the clock source for the a/d converter , which originates from the system clock f sys , can be chosen to be either f sys or a subdivided version of f sys . the division ratio value is determined by the adck2~adck0 bits in the adcr1 register . although the a/d clock source is determined by the system clocky , f sys , and by bits adck2~adck0, there are some limitations on the maximum a/ d clock source speed that can be selected. as the minimum value of permissible a/d clock period, t adck , is 0.5s, care must be taken for system clock frequencies equal to or greater than 5mhz. for example, if the system clock operat es at a frequency of 5mhz, the adck2~adck0 bits should not be set to "000"and "001". doing so will give a/d clock periods that are less than the minimum a/d clock period which may result in inaccurate a/d conversion values. refer t o t he fol lowing t able for e xamples, wh ere va lues m arked wi th a n a sterisk * sh ow whe re, depending upon the device, special care must be taken, as the values may be less than the specifed minimum a/d clock period.
rev. 1.00 104 ? a ? 1 ?? ? 01 ? rev. 1.00 105 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu f sys a/d clock period (t ad ) adck2, adck1, adck0 =000 (f sys ) adck2, adck1, adck0 =001 (f sys /2) adck2, adck1, adck0 =010 (f sys /4) adck2, adck1, adck0 =011 (f sys /8) adck2, adck1, adck0 =100 (f sys /16) adck2, adck1, adck0 =101 (f sys /32) adck2, adck1, adck0 =110 (f sys /64) adck2, adck1, adck0 =111 5 ? hz ? 00ns* 400ns* 800ns 1.6s 3.2s 6.4s 12.8s undefned 10 ? hz 100ns* ? 00ns* 400ns* 800ns 1.6s 3.2s 6.4s undefned ? 0 ? hz 50ns* 100ns* ? 00ns* 400ns* 800ns 1.6s 3.2s undefned a/d clock period examples controlling t he powe r on/ off func tion of t he a/ d c onverter c ircuitry i s i mplemented usi ng t he adoff bi t i n t he adcr0 re gister. t his bi t m ust be z ero t o power on t he a/ d c onverter. i f t he adoff bit is zero then some power will still be consumed. in power conscious applications it is therefore recommended that the adoff is set high to reduce power consumption when the a/d converter function is not being used. the bo undary re gister pa irs, adhvdl /adhvdh a nd adl vdl/adlvdh c ontain pr eset va lues which can be compared with the a/d converted values in the adrl/adrh registers. v arious types of comparis ons can be made as defned by the adcl ve and adchve bits and an interrupt generated t o i nform t he syst em t hat e ither t he l ower or hi gher bo undary ha s be en e xceeded. t his function can be used to ensure that the motor current operates within safe working limits. summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/ d conversion process. ? step 1 select the required a/d conversion clock by correctly programming bits adck2~adck0 in the adcr1 register. ? step 2 enable the a/d by clearing the adoff bit in the adcr0 register to zero. ? step 3 select which channel is to be connected to the internal a/d converter by correctly programming the acs2~acs0 bits which are also contained in the adcr0 register. ? step 4 select which pins are to be used as a/d inputs and confgure them by correctly programming the correct bits in the pin share registers. ? step 5 select which trigger circuit is to be used by correctly programming the adsts bits in the adcr1. ? step 6 if the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the a/d converter interrupt function is active. the master inter rupt control bit, emi, and the a/d converter interrupt bit, aeoce, must both be set high to do this. ? step 7 if the step 5 selects adstr trigger circuit, the analog to digital conversion process can be initialised by setting the adstr bit in the adcr0 register from low to high and then low again. note that this bit should have been originally cleared to zero. if the step 5 selects pwm interrupt trigger delay circuit, the delay start function can be enabled by setting the dlstr bit in the adcr1 register.
rev. 1.00 104 ?a? 1?? ?01? rev. 1.00 105 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu ? step 8 to check when the analog to digital conversion process is complete, the eocb bit in the adcr0 register ca n be poll ed. the conversion proc ess is com plete when thi s bit goes l ow. when thi s occurs the a/d data register adrl and adrh can be read to obtain the conversion value. as an alternative method , if the interrupts are enabled and the stack is not full, the program can wait for an a/d interrupt to occur. note: when checking for the end of the conversion process, if the method of polling the eocb bit in the adcr0 register is used, the interrupt enable step above can be omitted. the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardw are will begin to carry out the conversion, d uring wh ich t ime t he p rogram c an c ontinue wi th o ther f unctions. t he t ime t aken f or t he a/d conversion is 16t adck where t adck is equal to the a/d clock period. 0 1 2 3 4 10 11 12 tdeoc adclk start eocb d[5:0] tdout adon tckl tckh tadck tst tstart ton 000 h toff a/d conversion timing programming considerations during m icrocontroller ope rations where t he a/d c onverter i s not be ing used, t he a/d i nternal circuitry can be switched of f to reduce power consumption, by setting bit adoff high in the adcr0 r egister. w hen t his h appens, t he i nternal a/ d c onverter c ircuits wi ll n ot c onsume p ower irrespective of what analog voltage is applied to their input lines. if the a/d converter input lines are used as normal i/os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. a/d transfer function as the device contains a 10-bit a/d converter , its full-scale converted digitised value is equal to 3ffh. since the full-scale analog input value is equal to the v voltage, this gives a single bit analog input value of v dd divided by 1024. 1 lsb = v / 1024 the a/d converter input voltage value can be calculated using the following equation: a/d input voltage = a/d output digital value v / 1024 the diagram shows the ideal transfer function between the analog input value and the digitised output val ue for t he a/ d conve rter. e xcept for t he di gitised ze ro val ue, t he subsequent digi tised values will change at a point 0.5 lsb below where they would change without the of fset, and the last full scale digitised value will change at a point 1.5 lsb below the v level.
rev. 1.00 106 ? a ? 1 ?? ? 01 ? rev. 1.00 107 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu             
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 ?    ?    ideal a/d transfer function a/d programming examples the following two programming examples illustrate how to setup and implement an a/d conversion. in t he fr st e xample, t he m ethod o f p olling t he e ocb b it i n t he adc r0 r egister i s u sed t o d etect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using an eocb polling method to detect the end of conversion clr a eoce ; disable adc interrupt mov a,03h mov a dcr1,a ; select f sys /8 as a/d clock clr a doff mov a,0c0h ; setup paps1 to confgure pins an0~an1 mov p aps1,a mov a,00h mov a dcr0 ; enable and connect an0 channel to a/d converter : start_conversion: c lr adstr ; high pulse on start bit to initiate conversion s et adstr ; reset a/d c lr adstr ; start a/d polling_eoc: s z e ocb ; poll the adcr0 register eocb bit to detect end ; of a/d conversion j mp polling_eoc ; continue polling m ov a,adrl ; read low byte conversion result value m ov adrl_buffer,a ; save result to user defned register m ov a,adrh ; read high byte conversion result value m ov adrh_buffer,a ; save result to user defned register : : jmp st art_conversion ; start next a/d conversion
rev. 1.00 106 ?a? 1?? ?01? rev. 1.00 107 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu xample: using the interrupt method to detect the end of conversion clr m f1e ; disable adc interrupt clr a eoce mov a,03h mov a dcr1,a ; select f sys /8 as a/d clock c lr a doff mov a,0c0h ; setup paps1 to confgure pins an0~an1 mov p aps1,a mov a,00h mov a dcr0,a ; enable and connect an0 channel to a/d converter start_conversion: c lr adstr ; high pulse on start bit to initiate conversion s et adstr ; reset a/d c lr adstr ; start a/d c lr aeocf ; clear adc interrupt request fag s et aeoce ; enable adc interrupt se t mf1e ; enable multi_interrupt 1 s et emi ; enable global interrupt : : ; adc interrupt service routine adc_isr: m ov acc_stack,a ; save acc to user defned memory m ov a,status m ov status_stack,a ; save status to user defned memory : : m ov a,adrl ; read low byte conversion result value m ov adrl_buffer,a ; save result to user defned register m ov a,adrh ; read high byte conversion result value m ov adrh_buffer,a ; save result to user defned register : : exit_int_isr: m ov a,status_stack m ov status,a ; restore status from user defned memory m ov a,acc_stack ; restore acc from user defned memory reti
rev. 1.00 108 ? a ? 1 ?? ? 01 ? rev. 1.00 109 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu over-current detection the device contains an fully integrated over -current detect circuit which is used for motor protection. + _ opc? int _ is ap opa : av=1/5/ 10 / ?0 dac 8- bit op & compare ckt ap int _ is opa comparator 0 int _ad_ eoc int _ahl _ lim adc adr eoc ad hl / lv trigger int _ahl _ lim int trigger c0e adlvd/adhvd over-current detector block diagram over-current functional description the over -current functional block includes an amplifer , 10-bit a/d converter , 8-bit d/a converter and comparator . if an over -current situation is detected then the motor external drive circuit can be switched of f immediately to prevent damage to the motor . t wo kinds of interrupts are generated which can be used for over-current detection. ? a/d converter interrupt - int_ahl_lim ? comparator 0 interrupt - int_is over-current register description there are three registers to control the function and operation of the over current detection circuits, known a s opoms, opcm a nd op acal. t hese 8- bit re gisters de fne fu nctions suc h a s t he op a operation mode selection, op a calibration and comparison. opcm is an 8-bit dac register used for opa comparison.
rev. 1.00 108 ?a? 1?? ?01? rev. 1.00 109 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu opoms register bit 7 6 5 4 3 2 1 0 name c ? p0_eg1 c ? p0_eg0 opavs ? opavs1 opavs0 r/w r/w r/w r/w r/w r/w por 0 0 0 1 0 bit 7~6 cmp0_eg1~cmp0_eg0: defnes comparator active edge 00: disable comparator 0 and dac 01: rising edge 10: falling edge 11: dual edge bit 5~3 unimplemented, read as "0" bit 2~0 opavs2~opavs0: opa a v mode select 000: disable opa 001: a v=5 010: a v=10 011: a v=20 111: a v=1 note: it is need to enable an2/ap by setting pin share register when using opa function. opcm register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 8-bit opa comparison register bit 7 ~ bit 0 opacal register bit 7 6 5 4 3 2 1 0 name ars aof ? aof4 aof ? aof ? aof1 aof0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 ars: comparator input offset calibration reference select 0: comparator negative input 1: comparator positive input bit 5 aofm: normal or calibration mode select 0: opamp or comparator mode 1: offset calibration mode bit 4~0 aof4~aof0: comparator input offset voltage calibration control 00000: minimum 10000: center 11111: maximum
rev. 1.00 110 ? a ? 1 ?? ? 01 ? rev. 1.00 111 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu bldc motor control circuit this se ction d escribes h ow t he d evice c an b e u sed t o c ontrol b rushless dc mo tors, o therwise known as bldc motors. its high level of functional integration and fexibility of fer a full range of driving features for motor driving. functional description the pw m counter c ircuit o utput pw mo is h as a n a djustable pw m duty t o c ontrol t he o utput m otor power thus controlling the motor speed. changing the pwm frequency can be used to enhance the motor drive effciency or to reduce noise and resonance generated during physical motor operation. the internal m ask circuit is us ed to determine w hich pwm modulation s ignals are enabled or disabled for the mot or speed control . the pwm modulat ion si gnal ca n be out put bot h the upper arms, ga t/gbt/gct and the lower arms, gab/gbb/gcb, of the external gate driver t ransistor pairs under software control. the dead-t ime insertion circuit is used to ensure the upper and lower gate driver t ransistor pairs are not enabled simultaneously to prevent the occurrence of a virtual power short circuit. the dead time is selected under software control. the staggered circuit can force all the outputs to an of f status if the software detects an error condition which could be due to ext ernal fact ors such as esd problems or both upper and lower external ga te dr iver t ransistor p airs b eing si multaneously o n. t he po larity c ircuit c an se lect t he output polarity of the bldc motor output control port to support many dif ferent types of external mos gate drive device circuit combinations. the motor protect circuit includes many detection circuits for functions such as a motor stall condition, over current protection, external edge triggered pause pin, external level trigger fault pin etc. the hall sensor decoder circuit is a six-step system which can be used control the motor direction. twelve registers, e ach using 6 bits, are used to control the direction of the motor. t he motor forward, backward, brake and free functions are controlled by the hdcd/hdcr registers. the h a/hb/hc or sha/shb/shc can be selected as the hall sensor decoder circuit inputs.
rev. 1.00 110 ?a? 1?? ?01? rev. 1.00 111 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu 10- bit pw? counter ckt pw?r fpwm pw?ox ? pw?p _ int pw?d _ int x ? ?ptc 1 ?ask gat gab gbt gbb gct gcb over current protection stall protection s/w pw?bx ? ?cf dts pw?c dutrx ? prdr plc hdcd hc hb ha sha shb shc sa sb sc hd?s 0 1 hall sensor dcoder 1?x 6 register hdcr frs brke ?otor protect ckt hat hab hbt hbb h ct hcb p rotect hd _ en pw? complement polarit? dead time insert staggered circuit at ? ab ? bt ? bb ? ct ? cb ? at0 ab0 bt0 bb0 ct 0 cb 0 at 1 ab 1 bt 1 bb 1 ct 1 cb 1 brke ?cd ?ptc ? hall noise filter hall dela? ckt hchk _ nu? hnf _ ?sel ct? 16- int hdly _ ?sel ct? _ sel [1:0] pw??d pw??e bldc motor control block diagram note: gat, gab, gbt, gbb, gct, gcb == pwm0h, pwm0l, pwm1h, pwm1l, pwm2h, pwm2l . pwm counter control circuit the device includ es a 10-bit pwm generator . the pwm signal has both adjustable duty cycle and frequency that can be setup by programming 10-bit values into the corresponding pwm registers. 10 - bit pw? up / down counter ckt pw?r f pw? pw? 0~? pw?p _ int pw?d 0~?_ int pw?c dutr 0~? prdr pwm block diagram
rev. 1.00 11 ? ? a ? 1 ?? ? 01 ? rev. 1.00 11 ? ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu pw?p ( old ) pw?d _ ch 0( old ) pw?d _ ch 0( new ) pw?p ( new ) pw? edge - aligned ?ode pw?d _ ch 0( new ) pw?p ( new ) new pw? dut? new pw? period pw?o pwm edge-aligned mode timing diagram pw?p ( old ) pw?d _ ch 0( old ) pw?d _ ch 0( new ) pw?p ( new ) pw? center - aligned ?ode pw?d _ ch 0( new ) pw?p ( new ) new pw? dut? new pw? period pw?o center - align mode 1 center - align mode ? pwm center-aligned mode timing diagram pwm register description overall pwm operation is controlled by a series of registers. the dutr nl/dutrn h register pair is used for pwm duty control for adjustment of the motor output power . the prdrl/prdrh register pair are used together to form a 10-bit value to setup the pwm period for pwm frequency adjustment. be ing a ble t o c hange t he pw m fre quency i s use ful for m otor c haracteristic m atching for problems such as noise reduction and resonance. the pwmrl/pwmrh registers are used to monitor the pwm counter dynamic ally. the pwmon bit in the pwmc register is the 10-bit pwm counter on/of f bit. the pwm clock source for the pwm counter can be selected by pcks1~pcks0 bits in the pwmc register . the pwmms bits in the pwmc register determine the pwm alignment type, which can be either edge or centre type. it should be noted that the order of writing data to pwm register is msb.
rev. 1.00 11 ? ?a? 1?? ?01? rev. 1.00 11 ? ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu ? pwmc register bit 7 6 5 4 3 2 1 0 name pw ?? s1 pw ?? s0 pcks1 pcks0 pw ? on itc ? s1 itc ? s0 pw ? ld r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pwmms: pwm mode select bit 0x: edge-aligned mode, 10: centre-aligned mode 1 11: centre-aligned mode 2 bit 5~4 pcks1, pcks0: clock source of the pwm counter select 000: f pwm , pwm frequency min.=20khz, f pwm base on 20mhz 001: f pwm /2, pwm frequency min.=10khz 010: f pwm /4, pwm frequency min.=5khz 011: f pwm /8, pwm frequency min.=2.5khz bit 3 pwmon: pwm circuit on/off control 0: off 1: on this bit controls the overall on/of f function of the pwm. setting the bit high enables the counter to run, clearing the bit disables the pwm. clearing this bit to zero will stop t he c ounter fr om c ounting a nd t urn of f t he pw m whi ch wi ll re duce i ts po wer consumption. bit 2~1 itcms1~itcms0: 00: disable center-aligned mode duty interrupt 01: center-aligned mode duty interrupt only in counter up condition 10: center-aligned mode duty interrupt only in counter down condition 11: center-aligned mode duty interrupt both in counter up or down condition bit 0 pwmld: pwm prdr&dutrx,x=0~2 register update bit 0: the registers value of prdr and dutrx, x=0~2 are never loaded to counter and comparator registers. 1: the prdr register will be load value to counter register after counter underfow, and hardware will clear by next clock cycle. ? dutr0l register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 10-bit pwm0 duty register low byte register 10-bit dutr0 register bit 7 ~ bit 0 ? dutr0h register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 10-bit pwm0 duty register high byte register 10-bit dutr0 register bit 9 ~ bit 8
rev. 1.00 114 ? a ? 1 ?? ? 01 ? rev. 1.00 115 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu ? dutr1l register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 10-bit pwm1 duty register low byte register 10-bit dutr1 register bit 7 ~ bit 0 ? dutr1h register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 10-bit pwm1 duty register high byte register 10-bit dutr1 register bit 9 ~ bit 8 ? dutr2l register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 10-bit pwm2 duty register low byte register 10-bit dutr2 register bit 7 ~ bit 0 ? dutr2h register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 10-bit pwm2 duty register high byte register 10-bit dutr2 register bit 9 ~ bit 8 ? prdrl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 10-bit pwm period register low byte register 10-bit prdr register bit 7 ~ bit 0 ? prdrh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 10-bit pwm period register high byte register 10-bit prdr register bit 9 ~ bit 8
rev. 1.00 114 ?a? 1?? ?01? rev. 1.00 115 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu ? pwmrl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 10-bit pwm counter register low byte register 10-bit pwm counter bit 7 ~ bit 0 ? pwmrh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 10-bit pwm counter high byte register 10-bit pwm counter bit 9 ~ bit 8 mask function the device includes a motor control mask function for increased control fexibility. polarity pwmb ir 2101x3 gate driver mat mab mbt mbb mct mcb pwmo hall sensor decoder 12x6 hat/ hab/ hbt/ hbb/ hct/ hcb mask gat gab gbt gbb gct gcb mcf plc dead time insert staggered circuit at2 ab2 bt2 bb2 ct2 cb2 at0 ab0 bt0 bb0 ct0 cb0 at1 ab1 bt1 bb1 ct1 cb1 mcd brke p rotect pwmmd pwmme mask function block diagram ?otor u v w power ?os ?oto hv ?at ?bt ?ct ?ab ?bb ?cb mask switching
rev. 1.00 116 ? a ? 1 ?? ? 01 ? rev. 1.00 117 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu functional description the inter nal mask circuit has three operation modes, which are known as the normal mode, brake mode and motor protect mode. ? normal mode in the normal mode, the motor speed control method is determined by the pwms/mpwe bits in the mcf register. when pwms =0, the bottom port pwm output selects transistor pair bottom arm gab/ gbb/ gcb. when pwms =1, the top port pwm output selects transistor pair top arm, ga t / gb t / gc t . when mpwe =0, the pwm output is disabled and a t0/bt0/ct0/ab0/bb0/cb0 are all on. when mpwe =1, the pwm output is enabled and a t0/bt0/ct0/ab0/bb0/cb0 can output a variable pwm signal for speed control. when mpwms=0, the pwm has a complementary output . when mpwms=1, the pwm has a non-complementary output . mskms=0: the mask mode selects h/w . mskms=1: the mask mode selects s/w . ? h/w mask mode complementary control, mpwms=0 pw ? s=0 hat hab at0 ab0 pw ? s=1 hat hab at0 ab0 0 0 0 0 0 0 0 0 0 1 pw ? b pw ? o 0 1 0 1 1 0 1 0 1 0 pw ? o pw ? b 1 1 0 0 1 1 0 0 pw ? s=0 hbt hbb bt0 bb0 pw ? s=1 hbt hbb bt0 bb0 0 0 0 0 0 0 0 0 0 1 pw ? b pw ? o 0 1 0 1 1 0 1 0 1 0 pw ? o pw ? b 1 1 0 0 1 1 0 0 pw ? s=0 hct hcb ct0 cb0 pw ? s=1 hct hcb ct0 cb0 0 0 0 0 0 0 0 0 0 1 pw ? b pw ? o 0 1 0 1 1 0 1 0 1 0 pw ? o pw ? b 1 1 0 0 1 1 0 0 non-complementary control, mpwms=1 pw ? s=0 hat hab at0 ab0 pw ? s=1 hat hab at0 ab0 0 0 0 0 0 0 0 0 0 1 0 pw ? o 0 1 0 1 1 0 1 0 1 0 pw ? o 0 1 1 0 0 1 1 0 0
rev. 1.00 116 ?a? 1?? ?01? rev. 1.00 117 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu pw ? s=0 hbt hbb bt0 bb0 pw ? s=1 hbt hbb bt0 bb0 0 0 0 0 0 0 0 0 0 1 0 pw ? o 0 1 0 1 1 0 1 0 1 0 pw ? o 0 1 1 0 0 1 1 0 0 pw ? s=0 hct hcb ct0 cb0 pw ? s=1 hct hcb ct0 cb0 0 0 0 0 0 0 0 0 0 1 0 pw ? o 0 1 0 1 1 0 1 0 1 0 pw ? o 0 1 1 0 0 1 1 0 0 ? s/w mask mode to control the mas k circuit, two registers know n as pwm me , pwmmd , mcf and mcd are provided. pwmme register is used for control pwm signal and pwmmd is used to determine the mos gate driver circuit is on or of f. note that setting pwms and m pwms or anything related to pwm function is effective to h/w or s/w mode. 0 1 ? ? 4 5 ?- phase inverter s?mbol ?ask complement ?ode example ?ask independent ?ode example current path (??0) pw?o pw?b a b c a b c a b c a b c a b c pw?o pw?b current path (5?0) pw?o pw?b current path (5??) pw?o pw?b current path (1??) 1 1 0 0 1 1 p?en 1 0 x x 0 0 p?d 1 1 1 1 0 0 p?en 1 0 0 0 x x p?d 1 1 1 1 0 0 p?en 0 0 1 0 x x p?d 0 0 1 1 1 1 p?en x x 1 0 0 0 p?d current path (??0) pw?o a b c a b c a b c a b c pw?o current path (5?0) pw?o current path (5??) pw?o current path (1??) 1 1 1 0 1 1 p?en 1 0 0 x 0 0 p?d 1 1 1 1 1 0 p?en 1 0 0 0 0 x p?d 1 1 1 1 1 0 p?en 0 0 1 0 0 x p?d 1 0 1 1 1 1 p?en 0 x 1 0 0 0 p?d mask s/w mode circuit note: 1. during masking enabled, when pwmxh and pwmxl are masked simultaneously , the two pins of each pair can not be set to "1" simultaneously , pmd .0 and p md.1, p md .2 and p md.3 , pmd .4 and p md.5 . i f they are all high in the same time, switch 2n and switch 2n+1 will output "0". 2. if pw m a nd c omplementary pw m a re e nabled si multaneously , o ne of t he t wo re gisters pw mxh a nd pwmxl output pwm and the other one can not be masked to "1" but output "0" automatically by hardware. 3. if the pwmxh and pwmxl are confgured as i/o function, then pwm mask function will be invalid.
rev. 1.00 118 ? a ? 1 ?? ? 01 ? rev. 1.00 119 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu s/w mask register description ? pwmme register bit 7 6 5 4 3 2 1 0 name p ? e5 p ? e4 p ? e ? p ? e ? p ? e1 p ? e0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as"0" bit 5 ~0 pme 5~pme0: pwm mask enable register 0: pwm generator signal is output to next stage. 1: pwm generator signal is masked and pmdn is output to next stage. the pwm generator signal will be masked when this bit is enabled. the corresponding pwmn channel will be output with pmd.n data. ? pwmmd register bit 7 6 5 4 3 2 1 0 name p ? d5 p ? d4 p ? d ? p ? d ? p ? d1 p ? d0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as"0" bit 5-0 pmd 5~pmd0: pwm mask data bit 0: output logic low to pwmn. 1: output logic high to pwmn. this data bit control the state of pwmn output pin, if corresponding pme = 1. ? brake mode the brake mode has the highest priority . when activated, the external gate driver t ransistor pair top arm will be off and the bottom arm will be on. the brake t ruth decode table is shown below. brke=1 at0 bt0 ct0 ab0 bb0 cb0 0 0 0 1 1 1 ? motor protect mode when the motor protect mode is activated, the external gate driver t ransistor pair can select the brake, where the top arm is of f and the bottom arm is on, or select free running where the top and bottom arm are both off. the protection decode table is shown below. protect =1 gat gbt gct gab gbb gcb f ? os=0 0 0 0 0 0 0 f ? os=1 0 0 0 1 1 1 for 6-step communication, if the u winding and w winding are on then turn off the v winding. if gat =1 and gab =0, turn on the u winding if gbt =0 and gbb =0, turn off the v w inding. if gct=pwmd and gcb=pwm, turn on the w winding and adjust the output power of the motor using the dutr register to control the speed.
rev. 1.00 118 ?a? 1?? ?01? rev. 1.00 119 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu ht 66f? 5??0 ?at ?ab ?bt ?bb ?ct ?cb ir ?101 x? gat gab gbt gbb gct gcb drive signal block diagram v v u v w ?oto hv ?at ?bt ?ct ?ab ?bb ?cb ?oto hv ?oto hv 1 0 0 0 pw?d pw? current direction ?otor motor winding connection register description the device has two registers connected with the mask function control. these are the mcf register which is used for control and the mcd register which is used to read the status of the gate driver outputs . ? mcf register bit 7 6 5 4 3 2 1 0 name ? sk ? s ? pw ? s ? pwe f ? os pw ? s r r/w r/w r/w r/w r/w por 0 0 1 0 0 bit 7 mskms: mask mode select 0: h/w mask mode 1: s/w mask mode bit 6~4 unimplemented, read as"0" bit 3 mpwms: mask pwm mode select 0: complementary 1: non-complementary
rev. 1.00 1 ? 0 ? a ? 1 ?? ? 01 ? rev. 1.00 1?1 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu bit 2 mpwe: pwm output control 0: pwm output disable (at0/bt0/ct0/ab0/bb0/cb0 can not output pwm) 1: pwm output enable (at0/bt0/ct0/ab0/bb0/cb0 can output pwm to control speed) bit 1 fmos: fault mask output select 0: a t0/bt0/ct0=0, ab0/bb0/cb0=0 1: a t0/bt0/ct0=0, ab0/bb0/cb0=1 bit 0 pwms: t op port/bottom port pwm select 0: select bottom port pwm output 1: select t op port pwm output ? mcd register bit 7 6 5 4 3 2 1 0 name gat gab gbt fhc fhb fha r/w r r r r r r por 0 0 0 0 0 0 bit 7~6 unimplemented, read as"0" bit 5~3 gat/gab/gbt: gate diver output monitor bit 2~0 fhc/fhb/fha: hc/hb/ha fltered outputs these signals are derived from the hc/hb/ha signals and fltered by the hall noise filter. other functions several other functions exist for additional motor control drive signal fexibility . these are the dead time function, staggered function and polarity function. polarit? pw?b ir ?101 x ? gate driver ?at ?ab ?bt ?bb ?ct ?cb pw?o hall sensor decoder 1? x 6 hat / hab / hbt / hbb / hct / hcb ?ask gat gab gbt gbb gct gcb ?cf dts plc dead time insert staggered circuit at ? ab ? bt ? bb ? ct ? cb ? at 0 ab 0 bt 0 bb 0 ct 0 cb 0 at 1 ab 1 bt 1 bb 1 ct 1 cb 1 ?cd brke protect pw??d pw??e dead time, staggered and polarity function block diagram dead time function during transistor pair switching, the dead t ime function is used to prevent both upper and lower transistor pairs from conducting at the same time thus preventing a virtual short circuit condition from occurring. the actual dead time value can be setup to be within a value from 0.3s to 5s which is selected by the application program. the dead t ime insertion circuit requires six independent output circuits: when the a t0/ab0/bt0/bb0/ct0/cb0 outputs experience a rising edge, then a dead t ime is inserted. when the a t0/ab0/bt0/bb0/ct0/cb0 outputs experience a falling edge, then the outputs remain unchanged.
rev. 1.00 1?0 ?a? 1?? ?01? rev. 1.00 1 ? 1 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu the dead-t ime insertion circuit is only during motor control. the dead t ime function is enabled/ disabled by the dte bit in the dts register. at 0? ab 0? bt 0? bb 0? ct 0? cb 0 dead - time insertion dead - time insertion dead - time insertion dead - time insertion 1. rising add dead - time insertion ?. falling unchange at 1? ab 1? bt 1? bb 1? ct 1? cb 1 dead time insertion timing a single register, dts, is dedicated for use by the dead t ime function. ? dts register bit 7 6 5 4 3 2 1 0 name dtcks1 dtcks0 dte d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 dtcks1, dtcks0 : dead-time clock source selection 00: f is f , f based on 20mhz 01: f is f /2 10: f is f /4 11: f is f /8 bit 5 dte: dead t ime enable 0: dead-time=0 1: dead-time = (dts[4:0]+1)/f bit 4~0 d4~d0: dead t ime register bit 4 ~ bit 0 dead-time counter. 5-bit dead-time value bits for dead-time unit. dead-time = (dts[4:0]+1)/f staggered function the s taggered f unction is us ed to force all output drive trans istors to an of f condition w hen a software error occurs or due to external factors such as esd. at1 ab1 at2 ab2 0 0 0 0 0 1 0 1 1 0 1 0 1 1 0 0 the default condition for the bldc motor control circuit is designed for default n-type transistor pairs. this means a "1" value will switch the transistor on and a "0"value will switch it off.
rev. 1.00 1 ?? ? a ? 1 ?? ? 01 ? rev. 1.00 1?? ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu polarity function this function allow s setup of the external gate drive transistor on/of f polarity status. a single register, plc, is used for overall control. ? plc register bit 7 6 5 4 3 2 1 0 name pcbc pctc pbbc pbtc pabc patc r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 pcbc: c pair bottom port gate output inverse control bit 4 pctc: c pair t op port gate output inverse control bit 3 pbbc: b pair bottom port gate output inverse control bit 2 pbtc: b pair t op port gate output inverse control bit 1 pabc: a pair bottom port gate output inverse control bit 0 patc: a pair t op port gate output inverse control bit value status 0 output not inverted 1 output inverted plc register values note that the default output pin gat/gab/gbt/gbb/gct/gcb status is high impedance. hall sensor decoder this device contains a fully integrated hall sensor decoder function which interfaces to the hall sensors in the bldc motor for directional and speed control. hall sensor decoder 1? x6 registers hdcd hc hb ha sha shb shc sa sb sc hd?s hdcr frs brke hat hab hbt hbb hct hcb ?ask at 0 ab 0 bt 0 bb 0 ct 0 cb 0 0 1 hdcen pw?o pw?b brke p rotect hall noise filter hall dela? ckt hchk _ nu? hnf _ ?sel ct? - int x ? hdly _ ?sel ct? _ sel [1:0] hall sensor decoder block diagram the hall sensor input signals are selected by setting the hdms bit high. if the hdms bit is zero then sha/shb/shc will be used instead of the actual hall sensor signals.
rev. 1.00 1?? ?a? 1?? ?01? rev. 1.00 1 ?? ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu hall sensor noise filter this d evice i ncludes a ha ll no ise fi lter f unction t o fl ter o ut t he e ffects o f n oise g enerated b y t he large switching currents of the motor driver . this generated noise may af fect the hall sensor inputs (h1/h2/h3), which in turn may result in incorrect hall sensor output decoding. hc hb ha + _ + _ + _ c?p ? c?p ? ha 1 hb 1 hc 1 c?p 1 hsel hall noise filter hnf _ ?sel fhc fhb fha hala int ? halb int ? halc int c1 en c? en c? en hchk _ nu? integ h1 h? h? ha 0 hb 0 hc 0 hall sensor noise fliter blick diagram several registers are used to control the noise flter . the hnf_en bit in the hnf_msel register is used as the overall enable/disable bit for the noise flter . it is necessary to enable cmp1, cmp2 and cmp3 hysteries function before the camparators is used during motor control sensorless applications. hnf_en bit status 0 noise filter off C ha/hb/hc not used 1 noise filter on hall sensor noise filter enable the sampling frequency of the hall noise flter is setup using the hfr_sel [3:0] bits. the hc h k_num [4:0] bits are used to setup the hall sensor input compare numbers. hch k_num [4:0] sampling space = anti-noise ability = hall delay-time. it should be noted that longer hall delay times will result in higher rotor speed feedback signal distortion.
rev. 1.00 1 ? 4 ? a ? 1 ?? ? 01 ? rev. 1.00 1?5 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu hall sensor delay function the hall sensor function in the device includes a hall delay function which can implement a signal phase forward or phase backward operation. the following steps, which should be executed before the hall decoder is enabled, show how this function is activated. ? step 1 set the hall decode table to select either the phase forward or phase backward function. ? step 2 select which tm is used to generate the delay t ime and set the selected tm to run in the compare match mode by programming the ctm_sel1~ctm_sel0 bits. ? step 3 use the hdl y_msel bit to select the hall delay circuit operating mode. the default value of hdly_msel is zero which will disable the hall delay circuit. if the hdl y_msel bit is set high, then the hall delay circuit will be enabled. ? step 4 enable the hall decoder using the hdcen bit. the following points should be noted regarding the hdly_msel bit. ? when this bit is low, buf1[2:0] and buf2[2:0] will be cleared to zero. ? when this bit is low, tm0/tm1/tm2 retain their original tm functions. ? when the bit is high, the tm which is selected by the delay function will be dedicated for use by the hall delay circuit. the original tm functions will still remain active except for the tnon bit which will be controlled automatically by the hardware. with regard to the tm functions the following steps should be taken before the delay function is enabled. ? keep tnon and tnp au = 0 ? the tm should be setup in the compare match mode ? tncclr=1, therefore the tm is cleared with a comparator a match condition. ? setup the delay time using tmna and tnckx. after the delay function is enabled, hdl y_msel will change from low to high. the delay time must not be more than one step tim e of the hall input, which has six steps, otherwise the output can not be anticipated, will drop out of step.
rev. 1.00 1?4 ?a? 1?? ?01? rev. 1.00 1 ? 5 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu hall sensor decoder 1? x 6 register buf ?[?:0] buf 1[?:0] d d d ct? - 16 ( t? 1) ct? - 10 ( t? 0) st? - 10 ( t? ?) hall noise filter hdcd ha hb hc hdly _ ?sel hat hab hbt hbb hct hcb ct? _ sel [1:0] sha shb shc hd?s hall delay circuit hdcen ha 0 hb 0 hc0 ha 1 hb 1 hc1 ha ? hb ? hc ? sa sb sc fha fhb fhc delay function block diagram ha 0 hb 0 hc 0 sa sb sc dela? time delay function timing
rev. 1.00 1 ? 6 ? a ? 1 ?? ? 01 ? rev. 1.00 1?7 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu motor control drive signals the direction of the bldc motor is controlled using the hdcr, hdcd registers and a series of hdct registers, hdct0~hdct1 1. when using the hall sensor decoder function, the direction can be determined using the frs bit and the brake can be controlled using the brke bit. both bits are in the hdcr register . six bits in the hdct0~hdct5 registers are used for the motor forward table, and six bits in the hdct6~hdct11 registers are used for the motor backward table. the accompanying tables show the truth tables for each of the registers. forward (hdcen=1 ? frs=0 ? brke=0) 60 degree 120 degree bit5 bit4 bit3 bit2 bit1 bit0 sa sb sc sa sb sc hat hab hbt hbb hct hcb 1 0 0 1 0 0 hdct0[5:0] 1 1 0 1 1 0 hdct1[5:0] 1 1 1 0 1 0 hdct ? [5:0] 0 1 1 0 1 1 hdct ? [5:0] 0 0 1 0 0 1 hdct4[5:0] 0 0 0 1 0 1 hdct5[5:0] hall sensor decoder forward truth table backward (hdcen=1 ? frs=1 ? brke=0) 60 degree 120 degree bit5 bit4 bit3 bit2 bit1 bit0 sa sb sc sa sb sc hat hab hbt hbb hct hcb 1 0 0 1 0 0 hdct6[5:0] 1 1 0 1 1 0 hdct7[5:0] 1 1 1 0 1 0 hdct8[5:0] 0 1 1 0 1 1 hdct9[5:0] 0 0 1 0 0 1 hdct10[5:0] 0 0 0 1 0 1 hdct11[5:0] hall sensor decoder backward truth table the truth tables for the brake functi on, hall decoder disable function and hall decoder error function are also shown below. brake (brke=1 ? hdcen=x ? frs=x) 60 degree 120 degree bit5 bit4 bit3 bit2 bit1 bit0 sa sb sc sa sb sc hat hab hbt hbb hct hcb v v v v v v 0 1 0 1 0 1 brake truth table hall decoder disable (hdcen=0) 60 degree 120 degree bit5 bit4 bit3 bit2 bit1 bit0 sa sb sc sa sb sc hat hab hbt hbb hct hcb v v v v v v 0 0 0 0 0 0 hall decoder disable truth table hall decoder error (hdcen=x) 60 degree 120 degree bit5 bit4 bit3 bit2 bit1 bit0 sa sb sc sa sb sc hat hab hbt hbb hct hcb 1 0 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 hall decoder error truth table the relationship between the data in the truth tables and how they relate to actual motor drive signals i s sho wn i n t he a ccompanying t iming di agram. t he fu ll 6 st ep c ycle fo r bo th fo rward a nd backward motor rotation is provided.
rev. 1.00 1?6 ?a? 1?? ?01? rev. 1.00 1 ? 7 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu s1 s? s? s4 s5 s6 s1 s? s? s4 s5 s6 hat s a s b s c hall sensor : 1?0 degree ?otor forward n s ha hb hc ?- pole ?otor ?otor u v w ?oto hv ?at ?bt ?ct ?ab ?bb ?cb present power ?os ?bt ?bb ?ct ?cb ?at ?ab ht 66 fm 5230 ir 2101 x3 hbt hct hbb hcb hab motor drive signal timing diagram C forward direction s1 s? s? s4 s5 s6 s1 s? s? s4 s5 s6 hall sensor : 1?0 degree ?otor backward n s ha hb hc ?- pole ?otor ?otor u v w ?oto hv ?at ?bt ?ct ?ab ?bb ?cb present power ?os ?bt ?bb ?ct ?cb ?at ?ab ht 66 fm 5230 ir 2101 x3 hat hbt hct hbb hcb hab s a s b s c motor drive signal timing diagram C backward direction
rev. 1.00 1 ? 8 ? a ? 1 ?? ? 01 ? rev. 1.00 1?9 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu hall sensor decoder register description the hdcr register is the hall sensor decoder control register , hdcd is the hall sensor decoder input data register , and hdct0~hdct1 1 are the hall sensor decoder tables. the hchk_num register is the hall noise filter check number register and hnf_msel is the hall noise filter mode select register . ? integ register bit 7 6 5 4 3 2 1 0 name hsel intcs1 intcs0 intbs1 intbs0 intas1 intas0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 hsel: ha/hb/hc source select 0: h1/h2/h3 1: cmp1/cmp2/cmp3 output bit 5~4 intcs1, intcs0: fhc interrupt edge control for intc 00 : disable 01 : rising edge trigger 10 : falling edge trigger 11 : dual edge trigger bit 3~2 intbs1, intbs0: fhb interrupt edge control for intb 00 : disable 01 : rising edge trigger 10 : falling edge trigger 11 : dual edge trigger bit 1~0 int as1, intas0: fha interrupt edge control for inta 00 : disable 01 : rising edge trigger 10 : falling edge trigger 11 : dual edge trigger ? hdcr register bit 7 6 5 4 3 2 1 0 name ct ? _sel1 ct ? _sel0 hdly_ ? sel hals hd ? s brke frs hdcen r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 1 0 0 0 0 bit 7~6 ctm_sel1~ctm_sel0: tm select of the hall delay circuit 00:tm0(10-bit ctm) 01:tm1(16-bit ctm) 10:tm2(10-bit stm) 11:unused bit 5 hdly_msel: hall delay circuit select 0: select original path 1: select hall delay circuit bit 4 hals: hall sensor decoder mode select 0: hall sensor 60 degree 1: hall sensor 120 degree bit 3 hdms: hall sensor decoder mode select 0: s/w mode 1: hall sensor mode bit 2 brke: motor brake control 0: a t/bt/ct/ab/bb/cb=v 1: a t/bt/ct=0, ab/bb/cb=1
rev. 1.00 1?8 ?a? 1?? ?01? rev. 1.00 1 ? 9 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu bit 1 frs: motor forward/backward select 0: forward 1: backward bit 0 hdcen: hall sensor decoder enable 0: disable 1: enable ? hdcd register bit 7 6 5 4 3 2 1 0 name shc shb sha r/w r/w r/w r/w por 0 0 0 bit 7~3 unimplemented, read as "0" bit 2 shc: s/w hall c bit 1 shb: s/w hall b bit 0 sha: s/w hall a ? hdctn register n=0~11 bit 7 6 5 4 3 2 1 0 name hatdn habdn hbtdn hbbdn hctdn hcbdn r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 hatd n: gat output state control bit 4 habd n: gab output state control bit 3 hbtd n: gbt output state control bit 2 hbbd n: gbb output state control bit 1 hctd n: gct output state control bit 0 hcbd n: gcb output state control bit value status 0 output is low 1 output is high output status ? hchk_num register bit 7 6 5 4 3 2 1 0 name hck_n4 hck_n ? hck_n ? hck_n1 hck_n0 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7~5 unimplemented, read as "0" bit 4~0 hck_n4 ~ hck_n0 : hall noise filter check number
rev. 1.00 1 ? 0 ? a ? 1 ?? ? 01 ? rev. 1.00 1?1 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu ? hnf_msel register bit 7 6 5 4 3 2 1 0 name hnf_en hfr_ sel ? hfr_ sel1 hfr_ sel0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as "0" bit 3 hnf_en: hall noise flter enable 0: disable(bypass) 1: enable bit 2~0 hfr_sel2 ~ hfr_sel0 : hall noise flter clock source select 000:f /2 001:f /4 010:f /8 011:f /16 100:f /32 101:f /64 110:f /128 111:unused motor protection function motors normally require lar ge currents for their operation and as such need to be protected from the p roblems o f e xcessive d rive c urrents, m otor st alling e tc t o r educe m otor d amage o r f or sa fety reasons. this device includes a range of protection and safety features. ?ask at 0 ab 0 bt 0 bb 0 ct 0 cb 0 ?otor protect ckt opa & compare ckt ap capt? h1 ?ptc 1 h? h? p rotect int _ ahl _ lim int _ is capt? _ cmp capt? _ over ?ptc ? protection function block diagram
rev. 1.00 1?0 ?a? 1?? ?01? rev. 1.00 1 ? 1 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu pswd d reset opa & compare ckt ahlhe int _ahl_ lim ishe protect q int _ is capt? _cmp capche capt? capohe capt? _ over cacps=1 capops=1 isps=0 pswps=1 pswe pswps=0 ahlps=1 dela? ckt ahlps=0 protection function control motor protection function description this device provides three kinds of protection features, allowing action to be taken to protect the motor from damage or to provide additional safety. the protection features are: ? stall detection function ? over current protection ? turn off the motor using software when the motor protection circuit is on, the external gate drive transistor pair can be put into two different protection modes. the frst is the brake mode which is where the top arm is of f and the bottom arm is on, and the second is the free running mode where both top and bottom arms are off. the fmos bit in the mcf register determines which type is used. the motor protect ion circuit operat es in two modes, which is selected by the mptc2 register . one mode is the fault mode and the other is pause mode. in the fault mode, activating the protect function is determined by the trigger source starting status. ending the protect function is determined by the trigger source disarming status. in the pause mode, turning on the protect function is determined by the trigger source. ending the protection function is determined by software.
rev. 1.00 1 ?? ? a ? 1 ?? ? 01 ? rev. 1.00 1?? ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu current protection function the devic e uses an internal op a with a gain of 10, a high speed (2 m s) 10-bita/d converter , an 8-bit d/a converter and a comparator to measure the motor current and to detect for excessive current values. if an over current situation should occur , then the external drive circuit must be shut down immediately to prevent motor damage. as the motor driver pcb will have rather lar ge amounts of noise, and as this noise will be amplifed by the opa, this can easily lead to false triggering. for this reason the fault mode must be used. for the mos current limiting mechanism int_ahl_li: when ahlhe=0 then the hardware mode is disable d, and when ahlhe=1 the hardware is enabled. the current limiting circuit is a hardware circuit, for which the a/d converter channel must select the operation amplifier if it is to be effective. ahlps=0 the protection circuit will allow the pwm output to immediately restart once the int_ ahl_lim interrupt has been reset. ahlps=1 the protection circuit will only allow the pwm output to restart on the next pwm period once the int_ahl_lim interrupt has been reset. mos ove r-current m echanism int _is: whe n ishe =0 t he ha rdware m ode i s di sabled a nd whe n ishe=1 the hardware mode is enabled. isps=0 then select the fault mode pw? counter hat~ hcb x 6 s1 s? s? s4 s5 s6 15 khz ~ 64 us gat ~ gcb (x6) (pw?o) time int_ adc ?os limited current protect : ( ahlhe =1; ahlps =1) start the next c?cle of the pw? output automaticl? b? hardware int_ adc pw? counter hat~ hcb x 6 s1 s? s? s4 s5 s6 15 khz ~ 64 us gat ~ gcb (x6) (pw?o) time int_ c?p ?os over current protection : ( ishe =1; isps =0) restart the pw? output must b? software int_ c?p over current
rev. 1.00 1?? ?a? 1?? ?01? rev. 1.00 1 ?? ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu motor stall detection function for 3-phase bldc applications with hall sensors, the 16-bit captm can be used to monitor int0a, int0b and int0c for rotor speed detection. the software will setup the captmah and captmal registers to monitor the hall sensor inputs int0a, int0b and int0c for motor speed control. if an abnormal situation exists, then a captm_cmp or captm_over interrupt will be generated. stall detect mechanism captm_cmp: when capche=0 disable the hardware mode and when capche =1 enable the hardware mode. the stall detect mechanism must use the pause mode. capcps=1. then select the pause mode. stall detect mechanism captm_over: when capohe=0 disable the hardware mode and when capohe=1, enable the hardware mode. capops=1, then select the pause mode. motor protection circuit register description there a re t wo re gisters, mpt c1 a nd mpt c2, whi ch a re use d for t he m otor prot ection c ontrol function. ? mptc1 register bit 7 6 5 4 3 2 1 0 name pswd pswe capohe capche ishe ahlhe r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 protect s/w mode data 0: pswd=0 1: pswd=1 bit 6 protect s/w mode enable 0: disable 1: enable bit 5 captm_over h/w mode enable 0: disable 1: enable bit 4 captm_cmp h/w mode enable 0: disable 1: enable bit 3 int_is h/w mode enable 0: disable 1: enable bit 2 int_ahl_lim h/w mode enable 0: disable 1: enable bit 1~0 unimplemented, read as "0"
rev. 1.00 1 ? 4 ? a ? 1 ?? ? 01 ? rev. 1.00 1?5 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu ? mptc2 register bit 7 6 5 4 3 2 1 0 name pswps ahlps isps capcps capops r/w r/w r/w r/w r/w r/w por 1 0 0 1 1 bit 7~5 unimplemented, read as "0" bit 4 pswps: pause/fault mode select 0: select fault mode 1: select pause mode bit 3 ahlps: int_ahl_lim pause/fault mode selection 0: protection circuit allows immediate restart of pwm output when the int_ahl_lim interrupt has been reset. 1: protection circuit only allows restart of pwm output when on the next pwm period when the int_ahl_lim interrupt has been reset. bit 2 isps: int_is pause/fault mode select 0: undefned, cannot be selected 1: select pause mode bit 1 capcps: captm_cmp pause/fault mode select 0: select fault mode 1: select pause mode bit 0 capops: captm_over pause mode select 0: undefned, cannot be selected 1: select pause mode
rev. 1.00 1?4 ?a? 1?? ?01? rev. 1.00 1 ? 5 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu i 2 c interface the i 2 c interface is used to communicate with external peripheral devices such as sensors, eeprom m emory e tc. or iginally d eveloped b y ph ilips, i t i s a t wo l ine l ow sp eed se rial i nterface for synchronous serial data transfer . the advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications.                         i 2 c master/slave bus connection i 2 c interface operation the i 2 c serial interface is a two line interf ace, a serial data line, sda, and serial clock line, scl. as many devices may be connected together on the same bus, their outputs are both open drain types. for this reason it is necessary that external pull-high resistors are connected to these outputs. note that no chip select line exists, as each device on the i 2 c bus is identifed by a unique address which will be transmitted and received on the i 2 c bus. when two device s communicate with each other on the bidirectional i 2 c bus, one is known as the master de vice a nd one a s t he sl ave de vice. bot h m aster a nd sl ave c an t ransmit a nd re ceive da ta, however, i t i s t he m aster de vice t hat ha s ove rall c ontrol of t he bus. for t his de vice, wh ich onl y operates in slave mode, there are two methods of transferring data on the i 2 c bus, the slave transmit mode and the slave receive mode. it i s sugge sted t hat t he use r sha ll not e nter t he m icro proc essor t o hal t m ode by a pplication program during processing i 2 c communication. if the pin is confgured to sda or scl function of i 2 c interface, the pin is confgured to open-collect input/output port and its pull-up function can be enabled by programm ing the related generic pull- up control register.                      
                                                    
rev. 1.00 1 ? 6 ? a ? 1 ?? ? 01 ? rev. 1.00 1?7 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu i 2 c registers there are four control registers associated with the i 2 c bus, iicc0, iicc1, iica and i2ct oc and one d ata r egister, i icd. t he i icd register, i s u sed t o st ore t he d ata b eing t ransmitted a nd r eceived o n the i 2 c bus. before the microcontro ller writes data to the i 2 c bus, the actual data to be transmitted must be placed in the iicd register . after the data is received from the i 2 c bus, the microcontroller can read it from the iicd register . any transmission or reception of data from the i 2 c bus must be made via the iicd register. register name bit 7 6 5 4 3 2 1 0 iicc0 i ? cdbnc1 i ? cdbnc0 i ? cen iicc1 iichcf iichaas iichbb iichtx iictxak iicsrw iicrnic iicrxak iicd iicdd7 iicdd6 iicdd5 iicdd4 iicdd ? iicdd ? iicdd1 iicdd0 iica iica6 iica5 iica4 iica ? iica ? iica1 iica0 i ? ctoc i ? ctoen i ? ctof i ? ctos5 i ? ctos4 i ? ctos ? i ? ctos ? i ? ctos1 i ? ctos0 i 2 c registers list iicc0 register bit 7 6 5 4 3 2 1 0 name i ? cdbnc1 i ? cdbnc0 i ? cen r/w r/w r/w r/w por 0 0 0 bit 7~4 unimplemented, read as "0" bit 3~2 i2cdbnc1~i2cdbnc0: i 2 c debounce t ime selection 00: no debounce 01: 2 system clock debounce 10: 4 system clock debounce 11: 4 system clock debounce bit 1 i2cen: i 2 c enable 0: disable 1: enable bit 0 unimplemented, read as "0" spi function could be turned of f or turned on by controlling the related pin-sharing control bit which decides the function of the io ports pin-shared the pins sda and scl. when the io ports pin-shared the pins sda and scl are chosen to the functions other than sda and scl by pin-sharing control bit, spi function is turned of f and its operating current will be reduced to a minimum value. in contrary, spi function is turned on when the io ports pin-shared the pins sda and scl are chosen to the pins sda and scl by controlling pin-sharing control bit.
rev. 1.00 1?6 ?a? 1?? ?01? rev. 1.00 1 ? 7 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu iicc1 register bit 7 6 5 4 3 2 1 0 name iichcf iichaas iichbb iichtx iictxak iicsrw iicrnic iicrxak r/w r r r r/w r/w r r/w r por 1 0 0 0 0 0 0 1 bit 7 iichcf: i 2 c bus data transfer completion fag 0: data is being transferred 1: completion of an 8-bit data transfer the i ichcf fa g i s t he d ata t ransfer fa g. t his fa g wi ll b e z ero wh en d ata i s b eing transferred. upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. below is an example of the fow of a two-byte iic data transfer. first, iic slave device receive a start signal from iic master and then iichcf bit is automatically cleared to zero. second, iic sl ave de vice fi nish re ceiving t he 1st da ta byt e a nd t hen iichcf bi t i s automatically set to one. third, user read the 1st data byte from iicd register by the application program and then iichcf bit is automatically cleared to zero. fourth, iic slave device finish receiving the 2nd data byte and then iichcf bit is automatically set to one and so on. finally, iic slave device receive a stop signal from iic master and then iichcf bit is automatically set to one. bit 6 iichaas: i 2 c bus address match fag 0: not address match 1: address match the iichass fag is the address match fag. this fag is used to determine if the slave device address is the same as the master transmit address. if the addresses match then this bit will be high, if there is no match then the fag will be low. bit 5 iichbb: i 2 c bus busy fag 0: i 2 c bus is not busy 1: i 2 c bus is busy the iichbb fag is the i 2 c busy fag. this fag will be "1" when the i 2 c bus is busy which will occur when a st art signal is detected. the fag will be set to " 0" when the bus is free which will occur when a stop signal is detected. bit 4 iichtx: select i 2 c slave device is transmitter or receiver 0: slave device is the receiver 1: slave device is the transmitter bit 3 iictxak: i 2 c bus transmit acknowledge fag 0: slave send acknowledge fag 1: slave do not send acknowledge fag the iictxak bit is the transmit acknowledge fag. after the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. the slave device must always set iictxak bit to "0" before further data is received. bit 2 iicsrw: i 2 c slave read/write fag 0: slave device should be in receive mode 1: slave device should be in transmit mode the ii csrw fl ag i s t he i 2 c sl ave r ead/write fl ag. t his fl ag de termines whe ther the master device wishes to transmit or receive data from the i 2 c bus. when the transmitted address and slave address is match, that is when the iichaas fag is set high, the slave device will check the iicsr w fag to determine whether it should be in transmit mode or receive mode. if the iicsr w fag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. when the iicsrw fag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data.
rev. 1.00 1 ? 8 ? a ? 1 ?? ? 01 ? rev. 1.00 1?9 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu bit 1 iicrnic: i 2 c running using internal clock control 0: i 2 c running using internal clock 1: i 2 c running not using internal clock the i 2 c module can run without using internal clock, and generate an interr upt if the iic i nterrupt i s e nabled, wh ich c an b e u sed i n sl eep mo de, i dle (slow) mo de, normal(slow) mode. bit 0 iicrxak: i 2 c bus receive acknowledge fag 0: slave receive acknowledge fag 1: slave do not receive acknowledge fag the iicrxak fag is the receiver acknowledge fag. when the iicrxak fag is "0", it means that a acknowledge signal has been received at the 9th clock , after 8 bits of data have been transm itted. when the sl ave device in the transm it mode, the sla ve device checks the iicrxak fag to determine if the master receiver wishes to receive the next byte. the slave transmitter will therefore continue sending out data until the iicrxak fag is "1". when this occurs, the slave transmitter will relea se the sda line to allow the master to send a stop signal to release the i 2 c bus. the iicd register is used to store the data being transmitted and received. the same register is used by bot h t he spi a nd i 2 c fun ctions. be fore t he de vice wr ites da ta t o t he i 2 c bus, t he a ctual da ta t o be transmitted must be placed in the iicd register . after the data is received from the i 2 c bus, the device can read it from the iicd register . any transmission or reception of data from the i 2 c bus must be made via the iicd register. iicd register bit 7 6 5 4 3 2 1 0 name iicdd7 iicdd6 iicdd5 iicdd4 iicdd ? iicdd ? iicdd1 iicdd0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x "x" unknown bit 7~0 iicdd7~iicdd0: iic data buffer bit 7~bit 0 iica register bit 7 6 5 4 3 2 1 0 name iica6 iica5 iica4 iica ? iica ? iica1 iica0 r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x "x" unknown bit 7~1 iica6~iica0: i 2 c slave address iic a6~ iica 0 is the i 2 c slave address bit 6 ~ bit 0. the iica register is the location where the 7-bit slave address of the slave device is stored. bits 7~ 1 of the iica register defne the device slave address. bit 0 is not defned. when a master device, which is connected to the i 2 c bus, sends out an address, which matches the slave address in the iica register, the slave device will be selected. bit 0 unimplemented, read as "0"
rev. 1.00 1?8 ?a? 1?? ?01? rev. 1.00 1 ? 9 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu                          
                                       ?    ?    ?  ?  ?          ?-?     ?                     ?   ? ?  ?  ?   ? ?     ??        ?        ?      ? ?      ?    ?   i 2 c block diagram i 2 c bus communication communication on the i 2 c bus requires four separate steps, a st art signal, a slave device address transmission, a data transmission and fnally a st op signal. when a st art signal is placed on the i 2 c bus, all devices on the bus will receive this signal and be notifed of the imminent arrival of data on the bus. the frst seven bits of the data will be the slave address with the frst bit being the msb. if the address of the slave device matches that of the transmitted address, the iichaas bit in the iicc1 register will be set and an i 2 c interrupt will be generated. after entering the interrupt service routine, the slave device must frst check the condition of the iichaas bit to determine whether the interrupt source originates from an address match or from the comple tion of an 8-bit data transfer . during a data transfer , note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/writ e bit whose value will be placed in the sr w bit. this bit will be checked by the slave device to determine whether to go into transmit or receive mode. before any transfer of data to or from the i 2 c bus, the microcontroller must init ialise the bus, the following are steps to achieve this: ? step 1 set confgure the pin-shared i / o ports to i 2 c pin function. (scl and sad). ? step 2 set i2cen bit in the iicc0 register to "1" to enable the i 2 c bus. ? step 3 write the slave address of the device to the i 2 c bus address register iica. ? step 4 set the iice interrupt enable bit of the interrupt control register to enable the i 2 c interrupt and multi-function interrupt.
rev. 1.00 140 ? a ? 1 ?? ? 01 ? rev. 1.00 141 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu                            
                         ? ??       ?   ?   ?-            ?         ? i 2 c bus initialisation flow chart i 2 c bus start signal the st art signal can only be generated by the master device connected to the i 2 c bus and not by the slave device. this st art signal will be detected by all devices connected to the i 2 c bus. when detected, this indicates that the i 2 c bus is busy and therefore the iichbb bit will be set. a st art condition occurs when a high to low transition on the sda line takes place when the scl line remains high. slave address the t ransmission o f a st art si gnal b y t he m aster wi ll b e d etected b y a ll d evices o n t he i 2 c b us. to determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the st art signal. all slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. if the address sent out by the maste r matche s the internal address of the microcontroller slave device, then an internal i 2 c bus interrupt signal wil l be generat ed. the next bit fol lowing the address, which is the 8th bit, defnes the read/write status and will be saved to the iicsr w bit of the iicc1 register . the slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. the slave device will also set the status fag iichaas when the addresses match. as an i 2 c bus interrupt can come from two sources, when the program enters the interrupt subroutine, the iichaas bit should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer . when a slave address is matche d, the device must be placed in either the transmit mode and then write data to the iicd register, o r i n t he r eceive m ode wh ere i t m ust i mplement a d ummy r ead f rom t he i icd r egister t o release the scl line. i 2 c bus read/write signal the iicsr w bit in the iicc1 register defnes whether the slave device wishes to read data from the i 2 c bus or write data to the i 2 c bus. the slave device should examine this bit to determine if it is to be a transmitter or a receiver . if the iicsr w fag is "1" then this indicates that the master device wishes to read data from the i 2 c bus, therefore the slave device must be setup to send data to the i 2 c bus as a transmitte r. if the iicsr w fag is "0" then this indicates that the master wishes to send data to the i 2 c bus, therefore the slave device must be setup to read data from the i 2 c bus as a receiver.
rev. 1.00 140 ?a? 1?? ?01? rev. 1.00 141 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu i 2 c bus slave address acknowledge signal after t he m aster ha s t ransmitted a c alling a ddress, a ny sla ve de vice on t he i 2 c bus, whose own internal a ddress m atches t he c alling a ddress, m ust g enerate a n a cknowledge si gnal. t he a cknowledge signal will inform the master that a slave device has accepted its calling address. if no acknowledge signal is received by the master then a st op signal must be transmitted by the master to end the communication. when the iichaas fag is high, the addresses have matched and the slave device must check the iicsr w fag to determine if it is to be a transmitter or a receiver . if the iic srw fag is high, the slave device should be setup to be a transmitter so the iichtx bit in the iicc1 register should be set to "1". if the iicsrw fag is low, then the microcontroller slave device should be setup as a receiver and the iichtx bit in the iicc1 register should be set to "0". i 2 c bus data and acknowledge signal the transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt o f i ts sl ave a ddress. t he o rder o f se rial b it t ransmission i s t he msb fr st a nd t he l sb l ast. after receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level "0", before it can receive the next data byte. if the slave transmitter does not recei ve an acknowledge bit signal from the master receiver , then the slave transmitter will release the sda line to allow the master to send a st op signal to release the i 2 c bus. the corresponding data will be stored in the iicd register. if setup as a transmitter , the slave device must frst write the data to be transmitted into the iicd register . if setup as a receiver , the slave device must read the transmitted data from the iicd register. when the slave receiver receives the data byte, it must generate an acknowledge bit, known as iictxak, o n t he 9 th c lock. t he sl ave d evice, wh ich i s se tup a s a t ransmitter wi ll c heck t he iicrxak bit in the iicc1 register to determine if it is to send another data byte, if not then it will release the sda line and await the receipt of a stop signal from the master.                                  

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                  - i 2 c communication timing diagram note: *when a slave address is matched, the device must be placed in either the transmit mode and then write data to the iicd register, or in the receive mode where it must implement a dummy read from the iicd register to release the i 2 c scl line.
rev. 1.00 14 ? ? a ? 1 ?? ? 01 ? rev. 1.00 14? ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu                      
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  i 2 c bus isr flow chart i 2 c time-out control in order to reduce the problem of i 2 c lockup due to reception of erroneous clock sources, a time-out function is provided. if the clock source to the i 2 c is not received then after a fxed time period, the i 2 c circuitry and registers will be reset. the time-out counter starts counting on an i 2 c bus "st art" & "address match" condition, and is c leared b y a n sc l f alling e dge. b efore t he n ext sc l f alling e dge a rrives, i f t he t ime e lapsed i s greater than the time-out s etup by the i2ct oc regis ter, then a time-out condition w ill occur . the time-out function will stop when an i 2 c "stop" condition occurs. when an i 2 c time-out counter overflow occurs , the counter w ill stop and the i2ct oen bit w ill be c leared t o z ero a nd t he i2ct of bi t wi ll be se t hi gh t o i ndicate t hat a t ime-out c ondition h as occurred. the time-out condition will also generate an interrupt which uses the i 2 c interrupt vector . when an i 2 c time-out occurs, the i 2 c internal circuitry will be reset and the registers will be reset into the following condition: register after i 2 c time-out iicd ? iica ? iicc0 no change iicc1 reset to por condition i 2 c registers after time-out
rev. 1.00 14? ?a? 1?? ?01? rev. 1.00 14 ? ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu the i2ct of f ag can be cleared by the application program. there are 64 time-out periods w hich can be selected using bits in the i2ctoc register. the time-out time is given by the formula: ((1~64) 32) / f sub . this gives a range of about 1ms to 64ms. note also that the lirc oscillator is continuously enabled . i2ctoc register bit 7 6 5 4 3 2 1 0 name i ? ctoen i ? ctof i ? ctos5 i ? ctos4 i ? ctos ? i ? ctos ? i ? ctos1 i ? ctos0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 i 2 c t ime-out control 0: disable 1: enable bit 6 t ime-out fag (set by time-out and clear by software) 0: no time-out 1: time-out occurred bit 5~0 t ime-out defnition i 2 c time-out clock source is f sub /32. i 2 c time-out time is given by: ([i2ctos5 : i2ctos0]+1) (32/f sub ) interrupts interrupts are an important part of any microcontroller s ystem. when an external event or an internal function such as a t imer module or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device contains several external interrupt and internal interrupts functions. the external interrupt is generated by the action of the external h1, h2, h3 and nfin pins, while the internal interrupts are generated by various internal functions such as the tms, comparators, 16-bit captm modul, time base, l vd, eeprom and the a/d converter. interrupt registers overall interrupt control, w hich bas ically means the s etting of reques t flags w hen certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is control led by a series of registers, located in the special purpose data memory , as shown in the accompanying table. the number of registers depends upon the device chosen but fall into three categories. t he frst i s t he int c0~intc2 re gisters whi ch se tup t he pri mary i nterrupts, t he se cond is the mfi0~mfi4 registers which setup the multi-function interrupts. finally there is an integ register to setup the external interrupt trigger edge type. each regist er contai ns a number of enable bit s to enable or disa ble individual regist ers as wel l as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an "e" for enable/disable bit or "f" for request fag.
rev. 1.00 144 ? a ? 1 ?? ? 01 ? rev. 1.00 145 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu function enable bit request flag notes global e ? i external interrupt 0 (hall sensor ha/hb/hc interrupt) halle hallf ? fi0 halae halaf hall noise filtered halbe halbf hall noise filtered halce halcf hall noise filtered external interrupt 1 (noise fliter interrupt ) int1e int1f nfin interrupt noise filtered comparator 0 c0e c0f time base tbe tbf a/d converter aeoce aeocf ali ? e ali ? f capt ? capoe capof capce capcf lvd lvde lvdf eepro ? write epwe epwf pw ? pw ? dne pw ? dnf n=0 ? 1 ?? pw ? pe pw ? pf ct ? t ? nae t ? naf n=0 ? 1 t ? npe t ? npf n=0 ? 1 st ? t ? nae t ? naf n= ? t ? npe t ? npf n= ? i ? c iice iicf ? ultifunction interrupt ? fne ? fnf n=0~4 interrupt register bit naming conventions interrupt register contents name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 integ hsel intcs1 intcs0 intbs1 intbs0 intas1 intas0 intc0 c0f int1f hallf c0e int1e halle e ? i intc1 epwf lvdf ? f1f tbf epwe lvde ? f1e tbe intc ? iicf ? f4f ? f ? f ? f ? f iice ? f4e ? f ? e ? f ? e ? fi0 halcf halbf halaf halce halbe halae ? fi1 capcf capof ali ? f aeocf capce capoe ali ? e aeoce ? fi ? pw ? pf pw ? d ? f pw ? d1f pw ? d0f pw ? pe pw ? d ? e pw ? d1e pw ? d0e ? fi ? t ? 1af t ? 1pf t ? 0af t ? 0pf t ? 1ae t ? 1pe t ? 0ae t ? 0pe ? fi4 t ?? af t ?? pf t ?? ae t ?? pe
rev. 1.00 144 ?a? 1?? ?01? rev. 1.00 145 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu integ register bit 7 6 5 4 3 2 1 0 name hsel intcs1 intcs0 intbs1 intbs0 intas1 intas0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 hsel: ha/hb/hc source select 0: h1/h2/h3 1: cmp1/cmp2/cmp3 output bit 5~4 intcs1, intcs0: fhc interrupt edge control for intc 00 : disable 01 : rising edge trigger 10 : falling edge trigger 11 : dual edge trigger bit 3~2 intbs1, intbs0: fhb interrupt edge control for intb 00 : disable 01 : rising edge trigger 10 : falling edge trigger 11 : dual edge trigger bit 1~0 int as1, intas0: fha interrupt edge control for inta 00 : disable 01 : rising edge trigger 10 : falling edge trigger 11 : dual edge trigger intc0 register bit 7 6 5 4 3 2 1 0 name c0f int1f hallf c0e int1e halle e ? i r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 c0f: comparator 0 interrupt request fag 0: no request 1: interrupt request bit 5 int1f: external 1 interrupt request fag 0: no request 1: interrupt request bit 4 hallf: hall sensor global interrupt request fag 0: no request 1: interrupt request bit 3 c0e: comparator 0 interrupt control 0: disable 1: enable bit 2 int1e: external 1 interrupt control 0: disable 1: enable bit 1 halle: hall sensor global interrupt control 0: disable 1: enable bit 0 emi: global interrupt control 0: disable 1: enable
rev. 1.00 146 ? a ? 1 ?? ? 01 ? rev. 1.00 147 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu intc1 register bit 7 6 5 4 3 2 1 0 name epwf lvdf ? f1f tbf epwe lvde ? f1e tbe r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 epwf : data eeprom interrupt request fag 0: no request 1: interrupt request bit 6 lvdf: lvd interrupt request fag 0: no request 1: interrupt request bit 5 mf1f: multi-function interrupt 1 request flag 0: no request 1: interrupt request bit 4 tbf: t ime base interrupt request fag 0: no request 1: interrupt request bit 3 epwe : data eeprom interrupt control 0: disable 1: enable bit 2 lvde: lvd interrupt control 0: disable 1: enable bit 1 mf1e: multi-function interrupt 1 control 0: disable 1: enable bit 0 tbe: t ime base interrupt control 0: disable 1: enabl intc2 register bit 7 6 5 4 3 2 1 0 name iicf ? f4f ? f ? f ? f ? f iice ? f4e ? f ? e ? f ? e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 i icf: i 2 c interrupt request flag 0: no request 1: interrupt request bit 6 mf4f: multi-function interrupt 4 request fag 0: no request 1: interrupt request bit 5 mf3f: multi-function interrupt 3 request fag 0: no request 1: interrupt request bit 4 mf2f: multi-function interrupt 2 request fag 0: no request 1: interrupt request bit 3 iice: i 2 c interrupt control 0: disable 1: enable bit 2 mf4e: multi-function interrupt 4 control 0: disable 1: enable bit 1 mf3e: multi-function interrupt 3 control 0: disable 1: enable bit 0 mf2e: multi-function interrupt 2 control 0: disable 1: enab le
rev. 1.00 146 ?a? 1?? ?01? rev. 1.00 147 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu mfi0 register bit 7 6 5 4 3 2 1 0 name halcf halbf halaf halce halbe halae r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 halcf: hall sensor c interrupt request fag 0: no request 1: interrupt request bit 5 halbf: hall sensor b interrupt request fag 0: no request 1: interrupt request bit 4 halaf: hall sensor a interrupt request fag 0: no request 1: interrupt request bit 3 unimplemented, read as "0" bit 2 halce: hall sensor c interrupt control 0: disable 1: enable bit 1 halbe: hall sensor b interrupt control 0: disable 1: enable bit 0 halae: hall sensor a interrupt control 0: disable 1: enable mfi1 register bit 7 6 5 4 3 2 1 0 name capcf capof ali ? f aeocf capce capoe ali ? e aeoce r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 capcf: captm compare match interrupt request fag 0: no request 1: interrupt request bit 6 capof: captm capture overfow interrupt request fag 0: no request 1: interrupt request bit 5 alimf: a/d converter eoc compare interrupt request fag 0: no request 1: interrupt request bit 4 aeocf: a/d converter interrupt request fag 0: no request 1: interrupt request bit 3 capce: captm compare match interrupt control 0: disable 1: enable bit 2 capoe: captm capture overfow interrupt control 0: disable 1: enable bit 1 alime: a/d converter eoc compare interrupt control 0: disable 1: enable bit 0 aeoce: a/d converter interrupt control 0: disable 1: enable
rev. 1.00 148 ? a ? 1 ?? ? 01 ? rev. 1.00 149 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu mfi2 register bit 7 6 5 4 3 2 1 0 name pw ? pf pw ? d ? f pw ? d1f pw ? d0f pw ? pe pw ? d ? e pw ? d1e pw ? d0e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 pwmpf: pwm period match interrupt request fag 0: no request 1: interrupt request bit 6 pwmd2f: pwm2 duty match interrupt request fag 0: no request 1: interrupt request bit 5 pwmd1f: pwm1 duty match interrupt request fag 0: no request 1: interrupt request bit 4 pwmd0f: pwm0 duty match interrupt request fag 0: no request 1: interrupt request bit 3 pwmpe: pwm period match interrupt interrupt control 0: disable 1: enable bit 2 pwmd2e: pwm2 duty match interrupt control 0: disable 1: enable bit 1 pwmd1e: pwm1 duty match interrupt control 0: disable 1: enable bit 0 pwmd0e: pwm0 duty match interrupt control 0: disable 1: en able mfi3 register bit 7 6 5 4 3 2 1 0 name t ? 1af t ? 1pf t ? 0af t ? 0pf t ? 1ae t ? 1pe t ? 0ae t ? 0pe r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tm1 af: tm1 comparator a match interrupt request fag 0: no request 1: interrupt request bit 6 tm1pf: tm1 comparator p match interrupt request fag 0: no request 1: interrupt request bit 5 tm0af: tm0 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 tm0pf: tm0 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 tm1ae: tm1 comparator a match interrupt control 0: disable 1: enable bit 2 tm1pe: tm1 comparator p match interrupt control 0: disable 1: enable bit 1 tm0ae: tm0 comparator a match interrupt control 0: disable 1: enable bit 0 tm0pe: tm0 comparator p match interrupt control 0: disable 1: enable
rev. 1.00 148 ?a? 1?? ?01? rev. 1.00 149 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu mfi4 register bit 7 6 5 4 3 2 1 0 name t ?? af t ?? pf t ?? ae t ?? pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 ~6 unimplemented, read as "0" bit 5 tm2af: tm2 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 tm2pf: tm2 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as "0" bit 1 tm2ae: tm2 comparator a match interrupt control 0: disable 1: enable bit 0 tm2pe: tm2 comparator p match interrupt control 0: disable 1: enable interrupt operation when the conditio ns for an interrupt event occur , such as a tm compare p or compare a match or a/d conversion completion etc, the relevant interrupt request fag will be set. whether the request fag actually generates a program jump to the relevant interrupt vector is determined by the condition of t he i nterrupt e nable bi t. if t he e nable bi t i s se t hi gh t hen t he progra m wi ll j ump t o i ts re levant vector; if the enable bit is zero then although the interrupt request fag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector . the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector . the microcontroller will then fetch its next instruction from this interrupt vector . the instruction at this vector will usually be a "jmp" which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a "reti", which retrieves the original program counter address from the st ack a nd a llows t he m icrocontroller t o c ontinue wi th n ormal e xecution a t t he p oint wh ere t he interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority . some interrupt sources have their own individual vector w hile others s hare the s ame multi-function interrupt vector . o nce an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically . this will prevent any further interrupt nesting from occurring. however, i f ot her i nterrupt re quests oc cur duri ng t his i nterval, a lthough t he i nterrupt wi ll not be immediately serviced, the request fag will still be recorded.
rev. 1.00 150 ? a ? 1 ?? ? 01 ? rev. 1.00 151 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu if an interrupt requires immediate servicing while the program is alread y in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is a pplied. al l o f t he i nterrupt r equest fa gs wh en se t wi ll wa ke-up t he d evice i f i t i s i n sl eep o r idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the device is in sleep or idle mode. nfin hallf int 1f halle int 1e 04h 08h c?p0 c0f c0e 0 ch interrupt name request flags enable bits ?aster enable vector e?i auto disabled in isr low halbf halbe halcf halce h1 halaf halae interrupts contained within ?ulti - function interrupts priorit? high xxe enable bits xxf request flag ? auto reset in isr legend xxf request flag ? no auto reset in isr ?4 h ?8 h ?f4f ?f4e ?f?f ?f?e ?ulti - function ? ?ulti - function 4 eepro? epwf epwe h? h? 1 ch i ? c iicf iice ?0h ?f?f ?f?e ?ulti - function ? pw?p pw?pf pw?pe pw?d0 pw?d0f pw?d0e pw?d1 pw?d1f pw?d1e pw?d? pw?d?f pw?d?e 10 h time base tbf tbe 14 h ?ulti - function 1 ?f1f ?f1e ahl_ lim ali?f ali?e aeocf aeoce capcf capce capt? _ over capof capoe adc eoc capt? _cmp 18h lvd lvdf lvde t? 0 a t? 0af t? 0ae t? 0 p t? 0pf t? 0pe t? 1 a t? 1af t? 1ae t? 1 p t? 1pf t? 1pe t? ? a t? ?af t? ?ae t? ? p t? ?pf t? ?pe ?ulti - function 0 e?i e?i e?i e?i e?i e?i e?i e?i e?i e?i ? ch e?i interrupt structure
rev. 1.00 150 ?a? 1?? ?01? rev. 1.00 151 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu external interrupt 0 the e xternal i nterrupt 0 , a lso k nown a s t he ha ll se nsor i nterrupt, i s a mu lti-function i nterrupt. i t is controlled by signal transitions on the pins, hall sensor input pins, h1, h2 and h3. an external interrupt re quest wi ll t ake pl ace whe n t he e xternal i nterrupt re quest fl ag, hal af , hal bf or halcf is set, which will occur when a transition, appears on the external interrupt pins. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the multi-function interrupt controlled bit, halle must frst be set. when t he mul ti-function i nterrupt c ontrolled bi t hal le i s e nabled a nd t he st ack i s not ful l, a nd either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts and the related multi-function request flag h allf, w ill be automatically res et, but the m ulti-function interrupt reques t flags , halaf,halbf,halcf, must be manually cleared by the application program . external interrupt 1 th e external interrupt 1 is controlled by signal transitions on the pin nfin. an external interrupt request will take place when the external interrupt request flag, int1f , is set, which will occurs when a transition appears on the external interrupt pin. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and respective external interrupt enable bit, int1e, must frst be set. when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector , will take place. when the interrupt is serviced, the external interrupt request fag, int1f, wi ll b e a utomatically r eset a nd t he e mi b it wi ll b e a utomatically c leared t o d isable o ther interrupts. note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt i nput. comparator interrupt the comparator interru pt is control led by the internal comparator 0 . a comparator interrupt request will take place when the comparator interrupt request fag, c0f , is set, a situation that will occur when the comparator output changes state. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and comparator interrupt enable bit, c0e, must frst b e se t. w hen t he i nterrupt i s e nabled, t he st ack i s n ot f ull a nd t he c omparator i nputs g enerate a compar ator output transition, a subroutine call to the comparator inte rrupt vector , will take place. when the interrupt is serviced, the comparator interrupt request fag, c0f, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. time base interrupt the function of the t im e base interrupt is to provide regular time signal in the form of an internal interrupt. it is controlled by the overflow signal from its timer function. when this happens its interrupt request fag, tbf will be set. t o allow the program to branch to its interrupt vector address, the global interrupt enable bit, emi and t ime base enable bit, tbe, must first be set. when the interrupt is enable d, the stack is not full and the t ime base overfow , a subroutine call to its vector location will take place. when the interrupt is serviced, the interrupt request flag, tbf , will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the t ime base interrupt is to provide an interrupt signal at fxed time periods. its clock source originates from the internal clock source f tb . this f tb input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the tbc register to obtain longer interrupt periods whose value ranges. the clock source that generates f tb , which in turn controls the t ime ba se interrupt period, can originate from several dif ferent sources, as shown in the system operating mode section.
rev. 1.00 15 ? ? a ? 1 ?? ? 01 ? rev. 1.00 15? ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu tbc register bit 7 6 5 4 3 2 1 0 name tbon tbck tb1 tb0 r/w r/w r/w r/w r/w por 0 0 1 1 bit 7 tb tb control 0: disable 1: enable bit 6 tb select f tb clock 0: f tbc 1: f sys /4 bit 5~4 select t ime base t ime-out period 00: 4096/f tb 01: 8192/f tb 10: 16384/f tb 11: 32768/f tb bit 3~0 unimplemented, read as "0"                  
      
 
 
 
  
 
 time base interrupt multi-function interrupt within this device are fve multi-function interrupts. unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the hall sensor interrupts, a/d interrupts, pwm module interrupts, captm interrupts, tm interrupts. a multi-function interrupt request will take place when any of the multi-function interrupt request fags, hallf and mf1f~mf4f are set. the multi-function interrupt fags will be set when any of their included functions generate an interrupt request fag. t o allow the program to branch to its respective i nterrupt ve ctor a ddress, wh en t he mu lti-function i nterrupt i s e nabled a nd t he st ack i s not full, and eithe r one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the relat ed multi-function request fag, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, i t m ust be not ed t hat, a lthough t he mul ti-function int errupt fa gs wi ll be a utomatically reset when the interrupt is serviced, the request fags from the original source of the multi-function interrupts, namely the hall sensor interrupts, a/d interrupts, pwm module interrupts, captm interrupts, t m int errupts, wi ll no t be a utomatically re set a nd m ust be m anually re set by t he application program.
rev. 1.00 15? ?a? 1?? ?01? rev. 1.00 15 ? ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu a/d converter interrupt the a/ d c onverter ha s t wo i nt errupts. al l of t hem a re c ontained i n mul ti-function i nterrupt. t he one is controlled by the termination of an a/d conversion process. an a/d converter interrupt request will take place when the a/d converter interrupt request fag, alimf , is set, which occurs when the a/d conversion process fnishes. the other is controlled by the adchve/adcl ve bit in the adcr1 regi ster and t he val ue i n t he adl vdh/adlvdl and adhvdh/adhvdl bounda ry control registers. an a/d converter interrupt request will take place after eoc comparing. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and a/d interrupt enable bit, aeoce or alime, must frst be set. when the interrupt is enabled, the stack is not full and the a/d conversion process has ended or after eoc comparing a subroutine call to the a/d converter interrupt vector , will take place. when the interrupt is serviced, the a/d converter interrupt fag, aeocf or alimf , will be automatically cleared. the emi bit will also be automatically cleared to disable othe r interrupts. pwm module interrupts the pwm module ha s four interru ps. all of them are contained in multi-function interrupt, which is known as pwm dn and pwmp . they are the duty or the period mac hing of the pwm module. a pwm interrupt request will take place when the pwm interrupt request fag, pwmd n f or pwmpf , is set, which occurs when the pwm duty or pwm period matches. when the interrupt is enabled, the stack is not full and pwm duty or pwm period maches, a subroutine call to this vector location will take place. when the interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts and the related multi-function request flag will be automatically reset, but the interrupt request fag, pwm dn f or pwmpf, must be manually cleared by the application program. captm module interrupt the captm mod ule has two interrupts. all of them are contained within the multi-function interrupt, wh ich a re k nown a s c aptm_over a nd c aptm_cmp. a c aptm i nterrupt r equest wi ll take place when the captm interrupts request fag, capof or capcf , is set, which occurs when captm capture overfows or compare maches. t o allow the program to branch to their respective interrupt vector address, the global interrupt enable bit, emi, and the captm interrupt enable bit, and mut i-function i nterrupt e nable bi t, m ust frst be se t. w hen t he i nterrupt i s e nabled, t he st ack is not full and ca ptm capture overfow s or compare ma t ches, a s ubroutine call to the res pective multi-function interrupt ve ctor, will take pl ace. when the capt m interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the capof and capcf fag will not be automatically cleared, it has to be cleared by the application program. tm interrupt the compact and standard t ype tms have two interrupts each. all of the tm interrupts are contained within the multi-function interrupts. for each of the compact t ype tm and standard type tms there are two interrupt request flags tnpf and tnaf and two enable bits tnpe and tnae. a tm interrupt request will take place when any of the tm request fags is set, a situation which occurs when a tm comparator p or a match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, respective tm interrupt enable bit, and relevant multi-function interrupt enable bit, mfne, must frst be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs, a subroutine call to the relevant multi-function interrupt vector locations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the related mfnf fag will be automatically cleared. as the tm interrupt request fags will not be automatically cleared, they have to be cleared by the application program.
rev. 1.00 154 ? a ? 1 ?? ? 01 ? rev. 1.00 155 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu eeprom interrupt an e eprom int errupt wi ll t ake pl ace whe n t he e eprom int errupt re quest fl ag, e pwf, i s se t, which occurs when an eeprom w rite cycle ends. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi and eeprom interrupt enable bit, epwe, must frst be set. when the interrupt is enabled, the stack is not full and an eeprom w rite cycle ends, a subroutine call to the respective eeprom interrupt vect or, will take place. when the eeprom interrupt is serviced, the interrupt request fag, epwf , will be automatically reset and the emi bit will be cleared to disable other interrupts lvd interrupt an l vd interrupt request will take place when the l vd interrupt request fag, l vdf, is set, which occurs when the low v oltage detector function detects a low power supply voltage. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and l ow v oltage int errupt e nable bi t, l vde, m ust frst be se t. w hen t he i nterrupt i s e nabled, t he stack is not full and a low voltage condition occurs, a subroutine call to the l vd interrupt vector , will take place. when the eeprom interrupt is serviced, the interrup t request fag, l vdf, will be automatically reset and the emi bit will be cleared to disable other interrupts. i 2 c interrupt a i 2 c interrupt request will take place when the i 2 c interrupt request fag, iic f, is set, which occurs when a byte of data has been received or transmitted by the i 2 c interf ace. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the serial interface interrupt enable bit, iic e, must frst be set. when the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the i 2 c interface, a subroutine call to the respective interrupt vector , will take place. when the i 2 c interface interrupt is serviced , the interrupt request fla g, iic f, wi ll be aut omatically rese t and t he emi bit wi ll be cl eared t o disabl e othe r interrupts. interrupt wake-up function each of the int errupt funct ions has the capa bility of waki ng up the mi crocontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request fag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions o n t he e xternal i nterrupt p ins, a l ow p ower su pply v oltage o r c omparator i nput c hange may cause their respective interrupt fag to be set high and consequent ly generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no ef fect on the interrupt wake-up function.
rev. 1.00 154 ?a? 1?? ?01? rev. 1.00 155 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu programming considerations by di sabling t he re levant i nterrupt e nable bi ts, a re quested i nterrupt c an be pre vented from be ing serviced, however , once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. where a certain interrupt is contained w ithin a m ulti-function interrupt, then w hen the interrupt service r outine i s e xecuted, a s o nly t he mu lti-function i nterrupt r equest f lags, hallf a nd mf1 f~mf4f, will be automatically cleared, the individual request fag for the function needs to be cleared by the application program. it is recommended that programs do not use the "call" instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately . if only one stack is left and the inte rrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every i nterrupt h as t he c apability o f wa king u p t he m icrocontroller wh en i t i s i n sl eep o r i dle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interru pt from waking up the microcontrol ler then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator , status register or other registers are altered by the interrupt service program, t heir c ontents shoul d be sa ved t o t he m emory a t t he be ginning of t he i nterrupt se rvice routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts.
rev. 1.00 156 ? a ? 1 ?? ? 01 ? rev. 1.00 157 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu low voltage detector C lvd the device has a low v oltage detector function, also know n as l vd. this enables the device to monitor the power supply voltage, v dd , and provides a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. the low v oltage detector also has the capability of generating an interrupt signal. lvd register the low voltage detector function is controlled using a single register with the name l vdc. three bits in this register , vl vd2~vlvd0, are used to select a fxed voltage below which a low voltage condition will be detemined. a low voltage condition is indicated when the l vdo bit is set. if the l vdo bit is low , this indicates that the v dd voltage is above the preset low voltage value. the lvden bit is used to control the overall on/of f function of the low voltage detector . setting the bit high will enable the low voltage detector . clearing the bit to zero will switch of f the internal low voltage detector circuits. as the low voltage detector will consume a certain amount of power, it may be desirable to switch of f the circuit when not in use, an important consideration in power sensitive battery powered applications. lvdc register bit 7 6 5 4 3 2 1 0 name lvdo lvden vlvd ? vlvd1 vlvd0 r/w r r/w r/w r/w r/w por 0 0 0 0 0 bit 7 ~ 6 unimplemented, read as "0" bit 5 lvd output flag 0: no low v oltage detect 1: low v oltage detect bit 4 low v oltage detector control 0: disable 1: enable bit 3 unimplemented, read as "0" bit 2~0 : select lvd v oltage 000: 3.6v 001: 3.6v 010: 3.6v 011: 3.6v 100: 3.6v 101: 3.6v 110: 3.6v 111: 3.6v
rev. 1.00 156 ?a? 1?? ?01? rev. 1.00 157 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu lvd operation the low v oltage detector function operates by comparing the pow er supply voltage, v dd , with a pre-specifed volta ge level stored in the l vdc register . this has a voltage of 3.6v . when the power supply voltage, v dd , falls below this pre-determined value, the l vdo bit will be set high indicating a low power supply voltage conditio n. the low v oltage detector function is supplied by a reference voltage which will be automatically enabled. when the device is powered down the low voltage detector will remain active if the l vden bit is high. after enabling the low v oltage detector , a time dela y t lvds should be allowe d for the circuitry to stabilise before reading the l vdo bit. note also that as the v dd voltage may rise and fall rather slowly , at the voltage nears that of v lvd , there may be multiple bit lvdo transitions.              lvd operation the low v oltage detector also has its own interrupt which is contained within one of the multi- function interrupts, providing an alternative means of low voltage detection, in addition to polling the l vdo bit. the interrupt will only be generated after a delay of t lvd after the l vdo bit has been set high by a low voltage condition. when the device is powered down the low v oltage detector will remain active if the l vden bit is high. in this case, the l v d f interrupt request fag will be set, causing an interrupt to be generated if v dd falls below the preset l vd voltage. this will cause the devic e to wake-up from the sleep or idle mode, however if the low v oltage detector wake up functi on is not required then the l v d f fag should be frst set high before the device enters the sleep or idle mode.
rev. 1.00 158 ? a ? 1 ?? ? 01 ? rev. 1.00 159 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu application circuits three phase bldc hall sensor solution (v b =24v) pc 0/ tp 0_0/ gat pc 1/ tp 0_1/ gab pc ?/ tp 1_0/ gbt pc ?/ tp 1_1/ gbb pa 1/ tck ?/ an ?/ ap pa ?/ tck 1/h1/c1p pa 7/ nfin / an 1 pa ?/ scl / ocdsck / icpck pa 0/ sda / ocdsda / icpda ht 66 fm 5230 ( 16 nsop ) vdd / avdd +5v vss / avss pc 4/ tp ?_0/ gct pc 5/ tp ?_1/ gcb speed control hall o /p gnd vo vi 7815 + 15 v v b = ?4 v gate driver ( tr . x1? ) + ?4 v power ?os switch (p ?804 x?) + ?4 v vb rs ?otor vb volt . det . speed out gnd vo vi 7805 +5v + 15 v pa 4/h?/[ sda ]/c?p/[c1n] pa 5/h?/[ scl ]/c?p pa 6/[c1n]/ an 0 three phase bldc hall sensorless solution (v b =24v) pc 0/ tp 0_0/ gat pc 1/ tp 0_1/ gab pc ?/ tp 1_0/ gbt pc ?/ tp 1_1/ gbb pa 1/ tck ?/ an ?/ ap pa ?/ tck 1/h1/c1p pa 7/ nfin / an 1 pb 0/ hao / an ? pb 1/ ctin / hbo / an 4 ht 66 fm 5230 ( 20 ssop ) vdd / avdd +5v vss / avss pc 4/ tp ?_0/ gct pc 5/ tp ?_1/ gcb speed control gnd vo vi 7815 + 15 v v b = ?4 v gate driver ( tr . x1? ) + ?4 v power ?os switch (p ?804 x?) + ?4 v vb rs ?otor vb volt . det . speed out gnd vo vi 7805 +5v + 15 v sensorless bias and rc filter circuit ?otor u/v/w pb ?/ tck 1/c1n pb ?/ hco / an 5 pa ?/ scl / ocdsck / icpck pa 0/ sda / ocdsda / icpda u/v/w pa 4/h?/[ sda ]/c?p/[c1n] pa 5/h?/[ scl ]/c?p pa 6/[c1n]/ an 0
rev. 1.00 158 ?a? 1?? ?01? rev. 1.00 159 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu single phase bldc hall sensor solution (v b =12v) pc 0/ tp 0_0/ gat pc 1/ tp 0_1/ gab pc ?/ tp 1_0/ gbt pc ?/ tp 1_1/ gbb pa 1/ tck ?/ an ?/ ap pa ?/ tck 1/h1/c1p pa 7/ nfin / an 1 pa ?/ scl / ocdsck / icpck pa 0/ sda / ocdsda / icpda ht 66 fm 5230 ( 16 nsop ) vdd / avdd +5v vss / avss speed control gnd vo vi 7805 gate driver ( tr . x?) power ?os (h- bridge ) rs vb volt . det . speed out +5v + 1? v vb vbs + 1? v hall +5v pc 4/ tp ?_0/ gct pc 5/ tp ?_1/ gcb + 1? v pa 4/h?/[ sda ]/c?p/[c1n] pa 6/[c1n]/ an 0 pa 5/h?/[ scl ]/c?p single phase bldc hall sensorless solution (v b =12v) pc 0/ tp 0_0/ gat pc 1/ tp 0_1/ gab pc ?/ tp 1_0/ gbt pc ?/ tp 1_1/ gbb pa ?/ tck 1/h1/c1p pa 7/ nfin / an 1 pb 0/ hao / an ? pb 1/ ctin / hbo / an 4 ht 66 fm 5230 ( 20 ssop ) vdd / avdd +5v vss / avss speed control vb volt . det . speed out pb ?/ tck 0/c1n pb ?/ hco / an 5 pa ?/ scl / ocdsck / icpck pa 0/ sda / ocdsda / icpda gnd vo vi 7805 +5v vb vbs + 1? v out 1 +5v out 0 gate driver ( tr . x?) + 1? v power ?os (h- bridge ) + 1? v pa 1/ tck ?/ an ?/ ap rs pc 4/ tp ?_0/ gct pc 5/ tp ?_1/ gcb out 1 out 0 pa 6/[c1n]/ an 0 pa 4/h?/[ sda ]/c?p/pc1n] pa 5/h?/[ scl ]/c?p
rev. 1.00 160 ? a ? 1 ?? ? 01 ? rev. 1.00 161 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that direc ts the microcontroller to perform certain operations. in the case of holtek microcontroller , a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two ins truction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator , most instructions would be i mplemented wi thin 0.5 s a nd bra nch or c all i nstructions woul d be i mplemented wi thin 1s. although instructions which require one more cycle to implement are generally limited to the jmp , call, ret , reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct j ump t o t hat ne w a ddress, one m ore c ycle wi ll be re quired. e xamples of suc h i nstructions would be "clr pcl" or "mov pcl, a". for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the t ransfer of da ta wi thin t he m icrocontroller progra m i s one of t he m ost fre quently use d operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the ac cumulator. one of t he m ost i mportant da ta t ransfer a pplications i s t o re ceive da ta from t he input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithm etic operations and data manipula tion is a necessary feature of most m icrocontroller a pplications. w ithin t he hol tek m icrocontroller i nstruction se t a re a ra nge of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ens ure correct handling of carry and borrow data w hen res ults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 1.00 160 ?a? 1?? ?01? rev. 1.00 161 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu logical and rotate operation the standard logical operations such as and, or, xor and cpl all have their own instruction within t he hol tek m icrocontroller i nstruction se t. as wi th t he c ase of m ost i nstructions i nvolving data m anipulation, d ata m ust p ass t hrough t he ac cumulator wh ich m ay i nvolve a dditional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. dif ferent rotate instructions exist depending on program requirements. rotate instructions are useful for serial port progra mming a pplications whe re da ta c an be rot ated from a n i nternal re gister i nto t he ca rry bit from where it can be examined and the necessary serial bit set high or low . another application which rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or t o a su broutine usi ng t he cal l i nstruction. t hey di ffer i n t he se nse t hat i n t he c ase of a subroutine call, the program mus t return to the ins truction immediately w hen the s ubroutine has been carried out. this is done by placing a return ins truction " ret" in the s ubroutine w hich w ill cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping of f point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is frst made regarding the c ondition of a c ertain da ta m emory or i ndividual bi ts. de pending upon t he c onditions, t he program will continue with the next instruction or skip over it and jump to the following instruction. these i nstructions a re t he ke y t o de cision m aking a nd bra nching wi thin t he progra m pe rhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the abili ty to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers . this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the "set [m].i" or "clr [m]. i" instructions respectively . the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is take n care of automatically when these bit operation instructions are used. table read operations data st orage i s norm ally i mplemented by usi ng re gisters. however , whe n worki ng wi th l arge amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory . t o overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by w hich this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the "hal t" i nstruction f or po wer-down o perations a nd i nstructions t o c ontrol t he o peration o f the w atchdog t imer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.00 16 ? ? a ? 1 ?? ? 01 ? rev. 1.00 16? ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a ? [m] add data ? emor ? to acc 1 z ? c ? ac ? ov add ? a ? [m] add acc to data ? emor ? 1 note z ? c ? ac ? ov add a ? x add immediate data to acc 1 z ? c ? ac ? ov adc a ? [m] add data ? emor ? to acc with carr ? 1 z ? c ? ac ? ov adc ? a ? [m] add acc to data memor ? with carr ? 1 note z ? c ? ac ? ov sub a ? x subtract immediate data from the acc 1 z ? c ? ac ? ov sub a ? [m] subtract data ? emor ? from acc 1 z ? c ? ac ? ov sub ? a ? [m] subtract data ? emor ? from acc with result in data ? emor ? 1 note z ? c ? ac ? ov sbc a ? [m] subtract data ? emor ? from acc with carr ? 1 z ? c ? ac ? ov sbc ? a ? [m] subtract data ? emor ? from acc with carr ?? result in data ? emor ? 1 note z ? c ? ac ? ov daa [m] decimal adjust acc for addition with result in data ? emor ? 1 note c logic operation and a ? [m] logical and data ? emor ? to acc 1 z or a ? [m] logical or data ? emor ? to acc 1 z xor a ? [m] logical xor data ? emor ? to acc 1 z and ? a ? [m] logical and acc to data ? emor ? 1 note z or ? a ? [m] logical or acc to data ? emor ? 1 note z xor ? a ? [m] logical xor acc to data ? emor ? 1 note z and a ? x logical and immediate data to acc 1 z or a ? x logical or immediate data to acc 1 z xor a ? x logical xor immediate data to acc 1 z cpl [m] complement data ? emor ? 1 note z cpla [m] complement data ? emor ? with result in acc 1 z increment & decrement inca [m] increment data ? emor ? with result in acc 1 z inc [m] increment data ? emor ? 1 note z deca [m] decrement data ? emor ? with result in acc 1 z dec [m] decrement data ? emor ? 1 note z rotate rra [m] rotate data ? emor ? right with result in acc 1 none rr [m] rotate data ? emor ? right 1 note none rrca [m] rotate data ? emor ? right through carr ? with result in acc 1 c rrc [m] rotate data ? emor ? right through carr ? 1 note c rla [m] rotate data ? emor ? left with result in acc 1 none rl [m] rotate data ? emor ? left 1 note none rlca [m] rotate data ? emor ? left through carr ? with result in acc 1 c rlc [m] rotate data ? emor ? left through carr ? 1 note c
rev. 1.00 16? ?a? 1?? ?01? rev. 1.00 16 ? ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu mnemonic description cycles flag affected data move ? ov a ? [m] ? ove data ? emor ? to acc 1 none ? ov [m] ? a ? ove acc to data ? emor ? 1 note none ? ov a ? x ? ove immediate data to acc 1 none bit operation clr [m].i clear bit of data ? emor ? 1 note none set [m].i set bit of data ? emor ? 1 note none branch j ? p addr jump unconditionall ? ? none sz [m] skip if data ? emor ? is zero 1 note none sza [m] skip if data ? emor ? is zero with data movement to acc 1 note none sz [m].i skip if bit i of data ? emor ? is zero 1 note none snz [m].i skip if bit i of data ? emor ? is not zero 1 note none siz [m] skip if increment data ? emor ? is zero 1 note none sdz [m] skip if decrement data ? emor ? is zero 1 note none siza [m] skip if increment data ? emor ? is zero with result in acc 1 note none sdza [m] skip if decrement data ? emor ? is zero with result in acc 1 note none call addr subroutine call ? none ret return from subroutine ? none ret a ? x return from subroutine and load immediate data to acc ? none reti return from interrupt ? none table read tabrd [m] read table to tblh and data ? emor ? ? note none tabrdl [m] read table (last page) to tblh and data ? emor ? ? note none miscellaneous nop no operation 1 none clr [m] clear data ? emor ? 1 note none set [m] set data ? emor ? 1 note none clr wdt clear watchdog timer 1 to ? pdf clr wdt1 pre-clear watchdog timer 1 to ? pdf clr wdt ? pre-clear watchdog timer 1 to ? pdf swap [m] swap nibbles of data ? emor ? 1 note none swapa [m] swap nibbles of data ? emor ? with result in acc 1 none halt enter power down mode 1 to ? pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. f or the " clr wd t1" and " clr wd t2" ins tructions the t o and p df flags may be af fected by the execution status. the t o and pdf flags are cleared after both "clr wdt1" and "clr wdt2" instructions are consecutively executed. otherwise the t o and pdf fags remain unchanged.
rev. 1.00 164 ? a ? 1 ?? ? 01 ? rev. 1.00 165 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu instruction defnition adc a,[m] add d ata m emory to a cc w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] + c affected f ag(s) ov, z , a c, c adcm a,[m] add a cc to d ata m emory w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] + c affected f ag(s) ov, z , a c, c add a,[m] add d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] affected f ag(s) ov, z , a c, c add a,x add im mediate data to a cc description the c ontents o f t he a ccumulator a nd t he s pecifed im mediate data a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + x affected f ag(s) ov, z , a c, c addm a,[m] add a cc to d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] affected f ag(s) ov, z , a c, c and a,[m] logical a nd d ata m emory t o a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd [ m] affected f ag(s) z and a,x logical a nd im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b it w ise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd x affected f ag(s) z andm a,[m] logical a nd a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc and [ m] affected f ag(s) z
rev. 1.00 164 ?a? 1?? ?01? rev. 1.00 165 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu call addr subroutine c all description unconditionally c alls a s ubroutine a t t he s pecifed a ddress. th e p rogram c ounter t hen increments b y 1 to o btain t he a ddress o f t he n ext i nstruction w hich i s t hen p ushed o nto t he stack. t he sp ecifed a ddress is t hen loaded a nd t he p rogram c ontinues e xecution f rom t his new a ddress. a s t his instruction re quires a n a dditional op eration, it is a t wo c ycle instruction. operation stack p rogram counter + 1 program c ounter a ddr affected f ag(s) none clr [m] clear d ata m emory description each b it o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m] 00h affected f ag(s) none clr [m].i clear bi t o f d ata m emory description bit i o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m].i 0 affected f ag(s) none clr wdt clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re al l c leared. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt1 pre-clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re a ll c leared. n ote t hat t his instruction w orks in conjunction w ith c lr w dt2 a nd m ust b e e xecuted al ternately w ith c lr w dt2 to h ave effect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt2 w ill have no e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt2 pre-clear w atchdog t imer description the t o, p df f ags and t he w dt are all cleared. n ote t hat t his i nstruction w orks i n conjunction with c lr w dt1 a nd m ust b e e xecuted al ternately w ith c lr w dt1 to h ave e ffect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt1 w ill h ave n o e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df cpl [m] complement d ata m emory description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. operation [m] [m] affected f ag(s) z
rev. 1.00 166 ? a ? 1 ?? ? 01 ? rev. 1.00 167 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu cpla [m] complement d ata m emory w ith r esult i n a cc description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. th e c omplemented r esult i s s tored i n the a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] affected f ag(s) z daa [m] decimal-adjust a cc f or addition w ith r esult i n d ata m emory description convert t he c ontents o f t he a ccumulator v alue to a b cd ( binary c oded d ecimal) v alue resulting f rom t he p revious a ddition o f t wo b cd v ariables. i f t he low n ibble is greater t han 9 or i f a c f ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. o therwise t he l ow n ibble remains u nchanged. i f t he h igh n ibble i s g reater t han 9 o r i f t he c f ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. e ssentially, t he decimal c onversion i s p erformed b y a dding 00h, 0 6h, 6 0h o r 6 6h depending o n t he a ccumulator a nd f ag c onditions. o nly t he c f ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal b cd s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. operation [m] a cc + 00h or [m] a cc + 06 h o r [m] a cc + 60h o r [m] a cc + 66h affected f ag(s) c dec [m] decrement d ata m emory description data i n t he s pecifed d ata m emory i s d ecremented b y 1 . operation [m] [ m] ? 1 affected f ag(s) z deca [ m] decrement d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is d ecremented b y 1 . t he re sult is s tored in t he accumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] ? 1 affected f ag(s) z halt enter p ower down m ode description this i nstruction s tops t he p rogram e xecution a nd t urns o ff t he s ystem c lock. th e c ontents o f the d ata m emory a nd r egisters a re r etained. th e w dt a nd p rescaler a re c leared. th e p ower down f ag p df i s s et a nd t he w dt t ime-out f ag t o i s c leared. operation to 0 pdf 1 affected f ag(s) to, p df inc [m] increment d ata m emory description data in t he sp ecifed d ata m emory is incremented b y 1 . operation [m] [ m] + 1 affected f ag(s) z inca [m] increment d ata m emory wi th r esult i n a cc description data i n t he sp ecifed d ata m emory i s i ncremented b y 1 . th e re sult i s s tored i n t he a ccumulator. the c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] + 1 affected f ag(s) z
rev. 1.00 166 ?a? 1?? ?01? rev. 1.00 167 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu jmp addr jump u nconditionally description the c ontents o f t he p rogram c ounter a re re placed w ith t he sp ecifed a ddress. p rogram execution t hen c ontinues f rom t his n ew a ddress. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ew a ddress is loaded, it is a t wo c ycle instruction. operation program counter addr affected f ag(s) none mov a,[m] move d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. operation acc [ m] affected f ag(s) none mov a,x move im mediate data to a cc description the im mediate data s pecifed i s l oaded i nto t he a ccumulator. operation acc x affected f ag(s) none mov [m],a move a cc to d ata m emory description the c ontents o f t he a ccumulator a re c opied to t he s pecifed d ata m emory. operation [m] a cc affected f ag(s) none nop no o peration description no o peration i s p erformed. e xecution c ontinues w ith t he n ext i nstruction. operation no operation affected f ag(s) none or a,[m] logical o r d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise logical o r op eration. t he re sult is s tored in t he a ccumulator. operation acc a cc or [ m] affected f ag(s) z or a,x logical or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical o r operation. t he re sult is s tored in t he a ccumulator. operation acc a cc or x affected f ag(s) z orm a,[m] logical or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical o r operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc or [ m] affected f ag(s) z ret return from s ubroutine description the p rogram c ounter is re stored f rom t he s tack. p rogram e xecution c ontinues a t t he re stored a ddress. operation program counter s tack affected f ag(s) none
rev. 1.00 168 ? a ? 1 ?? ? 01 ? rev. 1.00 169 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu ret a,x return f rom su broutine and l oad im mediate data to a cc description the p rogram c ounter i s r estored f rom t he s tack a nd t he a ccumulator l oaded w ith t he s pecifed immediate data. p rogram e xecution c ontinues a t t he r estored a ddress. operation program counter s tack acc x affected f ag(s) none reti return from i nterrupt description the p rogram c ounter is re stored f rom t he s tack a nd t he interrupts a re re -enabled b y s etting t he emi b it. e mi i s t he m aster i nterrupt g lobal e nable b it. i f a n i nterrupt w as p ending w hen t he reti instruction is e xecuted, t he p ending in terrupt ro utine w ill b e p rocessed b efore re turning to t he m ain p rogram. operation program counter s tack emi 1 affected f ag(s) none rl [m] rotate d ata m emory l eft description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 [ m].7 affected f ag(s) none rla [m] rotate d ata m emory left w ith re sult in a cc description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 [ m].7 affected f ag(s) none rlc [m] rotate d ata m emory l eft t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated l eft b y 1 b it. b it 7 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 c c [ m].7 affected f ag(s) c rlca [m] rotate d ata m emory left t hrough c arry w ith re sult in a cc description data i n t he s pecifed d ata m emory and t he carry f ag are r otated l eft b y 1 b it. b it 7 r eplaces t he carry b it a nd t he o riginal c arry f ag i s r otated i nto t he b it 0 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 c c [ m].7 affected f ag(s) c rr [m] rotate d ata m emory r ight description the contents of t he s pecifed d ata m emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 [ m].0 affected f ag(s) none
rev. 1.00 168 ?a? 1?? ?01? rev. 1.00 169 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu rra [m] rotate d ata m emory right with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it w ith b it 0 rotated i nto b it 7 . th e r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he data m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 [ m].0 affected f ag(s) none rrc [m] rotate d ata m emory r ight t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 c c [ m].0 affected f ag(s) c rrca [m] rotate d ata m emory right th rough c arry with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 r eplaces the c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 c c [ m].0 affected f ag(s) c sbc a,[m] subtract d ata m emory from a cc wi th c arry description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sbcm a,[m] subtract d ata m emory from a cc wi th c arry a nd r esult i n d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he d ata m emory. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sdz [m] skip i f decrement d ata m emory i s 0 description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] ? 1 skip if [ m]=0 affected f ag(s) none
rev. 1.00 170 ? a ? 1 ?? ? 01 ? rev. 1.00 171 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu sdza [m] skip i f decrement d ata m emory i s z ero w ith r esult i n a cc description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] ? 1 skip if a cc=0 affected f ag(s) none set [m] set d ata m emory description each b it o f t he s pecifed d ata m emory i s s et t o 1 . operation [m] f fh affected f ag(s) none set [m].i set b it o f d ata m emory description bit i o f t he s pecifed d ata m emory i s s et t o 1 . operation [m].i 1 affected f ag(s) none siz [m] skip i f i ncrement d ata m emory i s 0 description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] + 1 skip if [ m]=0 affected f ag(s) none siza [m] skip if increment d ata m emory is z ero w ith re sult in a cc description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] + 1 skip if a cc=0 affected f ag(s) none snz [m].i skip i f b it i of d ata m emory i s n ot 0 description if b it i o f t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i 0 affected f ag(s) none sub a,[m] subtract d ata m emory from a cc description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] affected f ag(s) ov, z , a c, c
rev. 1.00 170 ?a? 1?? ?01? rev. 1.00 171 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu subm a,[m] subtract d ata m emory from a cc wi th r esult i n d ata m emory description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he d ata m emory. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] affected f ag(s) ov, z , a c, c sub a,x subtract im mediate data f rom a cc description the im mediate data s pecifed b y t he c ode i s s ubtracted f rom t he c ontents o f t he a ccumulator. the re sult is s tored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c fag w ill b e c leared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? x affected f ag(s) ov, z , a c, c swap [m] swap ni bbles of d ata m emory description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. operation [m].3~[m].0 ? [ m].7~[m].4 affected f ag(s) none swapa [m] swap ni bbles of d ata m emory w ith r esult i n a cc description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. th e result i s s tored i n t he a ccumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc.3~acc.0 [ m].7~[m].4 acc.7~acc.4 [ m].3~[m].0 affected f ag(s) none sz [m] skip i f d ata m emory i s 0 description if t he contents of t he s pecifed d ata m emory i s 0, t he following i nstruction i s s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m]=0 affected f ag(s) none sza [m] skip i f d ata m emory i s 0 w ith data m ovement to a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. i f t he v alue i s z ero, the f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. operation acc [ m] skip if [ m]=0 affected f ag(s) none sz [m].i skip i f b it i of d ata m emory i s 0 description if b it i o f t he sp ecifed d ata m emory is 0 , t he f ollowing instruction is s kipped. a s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m].i=0 affected f ag(s) none
rev. 1.00 17 ? ? a ? 1 ?? ? 01 ? rev. 1.00 17? ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu tabrd [m] read ta ble ( current p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( current p age) a ddressed b y t he t able p ointer ( tblp) is moved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdl [m] read t able (last p age) t o t blh a nd d ata m emory description the l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (tblp) i s mo ved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none xor a,[m] logical x or d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or [ m] affected f ag(s) z xorm a,[m] logical x or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical x or operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc xor [ m] affected f ag(s) z xor a,x logical x or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or x affected f ag(s) z
rev. 1.00 17? ?a? 1?? ?01? rev. 1.00 17 ? ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu package information note that the package information provided here is for consultation purposes only . as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package information. additional supplementary information with regard to pa ckaging is listed below. click on the relevant section to be transferred to the relevant website page. ? further package information (include outline dimensions, product t ape and reel specifcations) ? packing meterials information ? carton information ? pb free products ? green packages products
rev. 1.00 174 ? a ? 1 ?? ? 01 ? rev. 1.00 175 ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu 16-pin nsop (150mil) outline dimensions               ms-012 symbol dimensions in inch min. nom. max. a 0. ?? 8 0. ? 44 b 0.150 0.157 c 0.01 ? 0.0 ? 0 c 0. ? 86 0.40 ? d 0.069 e 0.050 f 0.004 0.010 g 0.016 0.050 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. max. a 5.79 6. ? 0 b ? .81 ? .99 c 0. ? 0 0.51 c 9.80 10. ? 1 d 1.75 e 1. ? 7 f 0.10 0. ? 5 g 0.41 1. ? 7 h 0.18 0. ? 5 0 8
rev. 1.00 174 ?a? 1?? ?01? rev. 1.00 175 ? a ? 1 ?? ? 01 ? HT66FM5230 brushless dc motor flash type 8-bit mcu 20-pin ssop (150mil) outline dimensions              symbol dimensions in inch min. nom. max. a 0. ?? 8 0. ? 44 b 0.150 0.158 c 0.008 0.01 ? c 0. ?? 5 0. ? 47 d 0.049 0.065 e 0.0 ? 5 f 0.004 0.010 g 0.015 0.050 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. max. a 5.79 6. ? 0 b ? .81 4.01 c 0. ? 0 0. ? 0 c 8.51 8.81 d 1. ? 4 1.65 e 0.64 f 0.10 0. ? 5 g 0. ? 8 1. ? 7 h 0.18 0. ? 5 0 8
rev. 1.00 176 ? a ? 1 ?? ? 01 ? rev. 1.00 pb ?a? 1?? ?01? HT66FM5230 brushless dc motor flash type 8-bit mcu cop ? right ? ? 01 ? b ? holtek se ? iconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however ? holtek assumes no responsibilit ? arising from the use of the specifcations described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warrant ? or representation that such applications will be suitable without further modification ? nor recommends the use of its products for application that ma ? present a risk to human life due to malfunction or otherwise. holtek's products are not authorized for use as critical components in life support devices or s ? stems. holtek reserves the right to alter its products without prior notifcation. for the most up-to-date information, please visit our web site at http://www.holtek.com.


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